QUICK START GUIDE
EPC9048C
EPC – THE LEADER IN GaN TECHNOLOGY |
| COPYRIGHT 2019 | | 2
DESCRIPTION
The EPC9048C development board shown in figure 1 is a 200 V maximum
device voltage, 15 A maximum output current, half bridge with onboard
gate drives, featuring two EPC2034C enhancement mode (eGaN®) field
effect transistors (FETs). The purpose of this development board is to
simplify the evaluation process of the EPC2034C eGaN FETs by including
all the critical components on a single board that can be easily connected
into any existing converter.
The EPC9048C development board is 1.5” x 2” and contains two EPC2034C
eGaN FETs in a half bridge configuration. As supplied, the high side gate
drive uses a digital isolator and both FETs use the Texas Instruments
UCC27611 gate driver. The board also contains all critical components
and layout for optimal switching performance. There are also various
probe points to facilitate simple waveform measurement and efficiency
calculation, as well as the option to add trimmer resistors for adjustable
deadtime to provide separate high and low side inputs, and an isolator for
the low side gate drive. A block diagram of the circuit is given in figure 2.
For more information on the EPC2034C please refer to the datasheet
available from EPC at www.epc-co.com. The datasheet should be read in
conjunction with this quick start guide.
QUICK START PROCEDURE
Development board EPC9048C is easy to set up to evaluate the
performance of EPC2034C eGaN FETs. Refer to figure 3 for proper connect
and measurement setup and follow the procedure below:
1. With power off, connect the input power supply bus to +V
IN
(J5, J6) and
ground / return to –V
IN
(J7, J8).
2. With power off, connect the switch node (SW) of the half bridge OUT
(J3, J4) to your circuit as required (half bridge configuration).
3. With power off, connect the gate drive power supply to +V
DD
(J1, Pin-1) and ground return to –V
DD
(J1, Pin-2).
4. With power off, connect the input PWM control signal to PWM
(J2, Pin-1) and ground return to any of the remaining J2 ground pins
(J2 Pin-2 or J2 Pin-4).
5. Turn on the gate drive supply – make sure the supply is between 7.5 V
and 12 V range.
6. Turn on the controller / PWM input source.
7. Turn on the bus voltage to the required value (do not exceed the
absolute maximum voltage) and probe switching node to see
switching operation.
8. Once operational, adjust the PWM control, bus voltage, and load within
the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE
. When measuring the high frequency content switch node, care must be taken
to provide an accurate high speed measurement. An optional two pin header (SWP1) is
included for switch node measurement. It is recommended to install measurement point on
backside of board to prevent contamination of the top side components.
For information about measurement techniques, please review the how to GaN series:
HTG09- Measurement
http://epc-co.com/epc/DesignSupport/TrainingVideos/HowtoGaN/
Figure 1: EPC9048C development board
Table 1: Performance Summary (T
A
= 25°C) EPC9048C
Symbol
Parameter
Conditions
Min
Max Units
V
DD
Gate Drive Input Supply Range
7.5
12
V
V
IN
Bus Input Voltage Range
(1)
160
V
I
OUT
Switch Node Output Current
(2)
15
A
V
PWM
PWM Logic Input Voltage
Threshold
Input ‘High’
Input ‘Low’
3.5
0
6
1.5
V
V
Minimum ‘High’ State
Input Pulse Width
V
PWM
rise and
fall time < 10ns
100
ns
Minimum ‘Low’ State Input
Pulse Width
(3)
V
PWM
rise and
fall time < 10ns
100
ns
(1) Maximum input voltage depends on inductive loading, maximum switch node ringing must be kept under
200 V for EPC2034C.
(2) Maximum current depends on die temperature – actual maximum current with be subject to switching
frequency, bus voltage and thermal cooling may be lower or higher. Please see the
for
further information.
(3) Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
