IDT VersaClock 6E 5P49V6965, Руководство пользователя

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8 ©2019 Integrated Device Technology, Inc. June 17, 2019
VersaClock
®
6E – 5P49V6965 and 5P49V6975 Programmer Board User Guide
11. After finishing the burning to OTP, the device can be tested as follows:
•
Unplug USB to remove power.
•
Place JP1 to make the device start in Hardware Select mode the next time USB (power) is plugged in again.
•
Place jumpers on JP14 and JP16 for selecting a specific configuration. No jumpers for configuration 0. Also see JP14 and JP16
functionality above. For checking configuration 0, it is not necessary to place a jumper on JP1. When starting in I2C mode,
configuration 0 is loaded by default.
•
Plug in USB to power up the board and the correct frequencies should be available on outputs, according to the configuration that
was burned to OTP.
Schematics
Programmer board schematics are shown on the following pages.
Figure 11. 5P49V6965/6975 Programmer Board Schematics – page 1
XTL
CLK1T
TP2
CLK2B
R45 0
1 2
CLKSEL_J
CLK1
C17
1u
1
2
C29
0.1u_NP
1 2
VDDO4
OUT2B
VDDD
R42 0
1 2
VDDO2
TP1
JP10
Header_4Pin
1
3
2
4
CLK0
R35 33
1 2
R31 33
1 2
C27
1u
1
2
VDDO0
R21 33
1 2
Output
Probe
Connections
C13
0.1u
1
2
USB_PWR
VDDO1
C16
0.1u
1
2
R27 33
1 2
R15
10K
1
2
JP9
Header_4Pin
1
3
2
4
C11
1u
1
2
JP3
VDDO1_NP
1 2
CLK4
U4
5P49V6965
CLKIN
1
CLKINB
2
XOUT
3
XIN/REF
4
VDDA
5
CLKSEL
6
SD
/O
E
7
SE
L1
/S
D
A
8
SE
L0
/S
C
L
9
VD
D
O
4
10
OU
T
4
11
OU
T
4B
12
OUT3B
13
OUT3
14
VDDO3
15
OUT2B
16
OUT2
17
VDDO2
18
OU
T
1B
19
OU
T
1
20
VD
D
O
1
21
VD
D
D
22
VD
D
O
0
23
OU
T
0_
S
E
L
B_
I2
C
24
e_
P
A
D
25
CLK0
R18 220
1 2
CLK1C
JP16
SCL/SEL0
1 2 3
R26 33
1 2
CLKINB
R14
0
1
2
CLK4B
R30 33
1 2
OUT1B
JP12
CLKSEL
1 2
CLK3
OUT1
R38
4.7k
1
2
C25
1u
1
2
CLK4
C26
0.1u
1
2
C23
0.1u
1
2
SEL0_SCL
VDDO3
VDDD
OUT4B
C20
10p(np)
1
2
CLK2B
R46 0
1 2
OUT3B
CLK1
VDDD
CLK2
PU
SDOE_J
JP13
OE
1 2
CLK1C
R20 33
1 2
CLK3B
CLK2
R36
1K
1 2
CLK1B
SDOE
C19
10nF
1 2
JP1
Mode
1
2
J2
SMA_STRAIGHT_pin_NP
GND
VDDO4
CLK3
MO
D
E
VDDO1
VDDD
R32 220
1 2
I2C
SDA
XIN_REF
GND
JP8
VDDO4_NP
1 2
SEL1_SDA
PU
C24
0.1u
1
2
XI
N
R41
10K
1
2
C22
1u
1
2
R24 220
1 2
X2
25MHz
1 3
2
4
VDDO3
CLKSEL
C28
47pF
1
2
JP7
Header_4Pin
1
3
2
4
C18
0.1u
1
2
R17 33
1 2
R28 220
1 2
OUT2
CLK1B
Optional
External
Power
JP2
VDDO0_NP
1 2
JP4
VDDO2_NP
1 2
VDDD
R40
10K
1
2
R33 220
1 2
OUT0
I2C
SCL
JP14
SDA/SEL1
1 2 3
J1
USB_PWR
R39
4.7k
1
2
J3
SMA_STRAIGHT_pin_NP
REF
VDDD
R34
2.2
1
2
JP17
Xtal / Clock
1
2
3
REF
JP5
VDDO0
1 2
R23
100
1
2
VDDD
R16 33
1 2
C15
1u
1
2
R25 220
1 2
SEL1_SDA_PIN
CLK4B
C30
0.1u_NP
1 2
R44 0
1 2
R29 220
1 2
C21
10p(np)
1
2
GND
OUT3
CLKIN
OUT4
CLK1T
C12
0.1u
1
2
VDDO2
R37
1K
1 2
R19 220
1 2
XOUT
USB_PWR
CLK3B
VDDO0
C14
1u
1
2
R43 0
1 2
SEL0_SCL_PIN
R22
100
1
2
JP6
VDDO3_NP
1 2
VDDA
JP11
Header_4Pin
1
3
2
4