JULY 13, 2016
8
VERSACLOCK
®
3S - 5P35021 Evaluation Board
Figure 8. Evaluation Board Schematic (IV)
Signal Termination Options
Termination options for Differential Output 1 - 2 in the evaluation board are displayed in
Figure 9
. The termination circuits are
designed to optionally terminate the output clocks in LVPECL, LVDS, LVCMOS and HCSL signal types by populating (or
not-populating) some resistors. DC or AC coupling of these outputs are also supported.
Table 5
and
Table 6
, below, tabulates component installations to support LVPECL, HCSL, LVCMOS and LVDS signal types for
OUTPUT1 - 2, respectively. Please note that by doing so, the output signals will be measured and terminated by an oscilloscope
with a 50
internal termination.
Figure 9. Output Termination Options
DIFF_CO/TO
DIFF_C1/T1