1. Board Design
14
Tsi381 Evaluation Board User Manual
60E2000_MA001_03
Integrated Device Technology
www.idt.com
1.4.5
PCI Vaux (PCI Auxiliary) Support
PCI connectors are provided with a 3.3V supply to the vaux pins only during operation. There is no
support for this power supply in standby mode. This feature is not documented in the Tsi381 evaluation
board schematic.
1.5
Clock Management
The Tsi381 requires up to two input clocks to operate:
•
25–66 MHz clock for PCI
•
100-MHz reference clock for PCIe
The PCI and PCIe input clocks are briefly discussed.
1.5.1
PCI
The evaluation board supports master and slave clocking for PCI.
•
Master – When in master mode, the Tsi381 generates the required PCI clock for all slots.
•
Slave – When in slave mode, an on-board selectable 25–66 MHz clock generator is used.
On-board resistor muxes are used to multiplex either Tsi381’s PCI clock or the external clock
generator.
1.5.1.1
PCIe
For PCIe clocking, a 100-MHz differential HCSL clock source is required. The clock source is
available in two forms:
•
Edge connector clock source – This clock source synchronizes the system SerDes with the Tsi381.
•
On-board 100-MHz reference – This clock source can separate the clock domains between the
bridge and the root complex.
The two PCIe clock sources are multiplexed with an analog multiplexer to select between the system
clock or on-board clock (see
Figure 3
).
