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IDT ADC1410S Series, Быстрый старт

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Integrated Device Technology 

Quick start ADC1410S, ADC1210S, ADC1010S series 

 

Quick start 

 

 

© IDT 2012. All rights reserved. 

Quick start 

Rev. 06 

— 2 July 2012 

23 of 27 

3.2.5.4  Histogram 

The histogram graph shows the distribution of output codes. This graph shows which 
code is present and if there is any missing code in the conversion range: 

 

 

Fig 17. 

SW_ADC_1_r02: “Acquisition” page, code histogram graph 

Press the “Autoscale” button to display the whole content. 

The table shows the range of output codes. 

Содержание ADC1410S Series

Страница 1: ...10S series Rev 06 2 July 2012 Quick start Document information Info Content Keywords PCB2001 2 demonstration board ADC converter input buffer Abstract This document describes how to use the demonstrat...

Страница 2: ...ved Quick start Rev 06 2 July 2012 2 of 27 Revision history Rev Date Description 1 20081001 Initial version 2 20090518 Update to PCB2001 2 3 20090610 Add SPI software description 4 20100519 Add HSDC e...

Страница 3: ...410S series typical configuration set up PRESENTED CONFIGURATION 2Vpp input full scale Single Sine wave clock signal Input common mode from IC Binary ADC output SPI Mode INPUT SIGNAL 2Vpp sinewave AC...

Страница 4: ...ation set up PRESENTED CONFIGURATION 2Vpp input full scale Single Sine wave clock signal Input common mode from IC Binary ADC output SPI Mode INPUT SIGNAL 2Vpp sinewave AC SYNTHESIZED SIGNAL GENERATOR...

Страница 5: ...ration set up PRESENTED CONFIGURATION 2Vpp input full scale Single Sine wave clock signal Input common mode from IC Binary ADC output SPI Mode INPUT SIGNAL 2Vpp sinewave AC SYNTHESIZED SIGNAL GENERATO...

Страница 6: ...D test point Digital ground TP2 DGND test point Analog ground 1 5 Input signals IN CLK The input clock signal can be either a sine wave or a LVCMOS signal To ensure a good evaluation of the device the...

Страница 7: ...y 2 s complement or gray format A Data Valid Output clock DAV is provided by the device for the data acquisition Table 3 Output signals Name Function View J4 Array connector ADC digital output D0 to D...

Страница 8: ...hnology Quick start ADC1410S ADC1210S ADC1010S series Quick start IDT 2012 All rights reserved Quick start Rev 06 2 July 2012 8 of 27 1 8 SPI program For more details on how to control device with SPI...

Страница 9: ...PLY I 3 2 A REFERENCE SIGNAL typical 10 MHz SIGNAL GENERATOR USB SPI MODULE PRESENTED CONFIGURATION acquisition board external reference signal LVDS DDR 16 bit input stream CMOS 2 16 bit channels inpu...

Страница 10: ...ation In this section the specific requirement for the use with ADC1410S demo board will be shown For more details on the HSDC EXTMOD01 DB please visit http www idt com 2 1 HSDC extension module hardw...

Страница 11: ...Device Technology Quick start ADC1410S ADC1210S ADC1010S series Quick start IDT 2012 All rights reserved Quick start Rev 06 2 July 2012 11 of 27 Fig 5 HSDC extension module HE14 CMOS hardware schemati...

Страница 12: ...ith CMOS outputs configuration for which connection is straightforward together with a supply extension module release A for the ADC1410S demo board Fig 6 Evaluation set up measurement with ADC1410S C...

Страница 13: ...nected to your system and display information as can be seen on following window Fig 7 SW_ADC_1_r02 start up screen IDT Banner Button will display your default internet browser to the IDT data convert...

Страница 14: ...eries Quick start IDT 2012 All rights reserved Quick start Rev 06 2 July 2012 14 of 27 Fig 8 SW_ADC_1_r02 Info page The HSDC EXTMOD is not yet initialized so the embedded PLL LMK03001 in this example...

Страница 15: ...ick start Rev 06 2 July 2012 15 of 27 3 2 1 ADC SPI programming Functional Registers page The page displays all SPI registers for ADC1410S ADC1210S and ADC1010S series Fig 9 SW_ADC_1_r02 ADC Functiona...

Страница 16: ...clicking on the Read all registers button and will display the result in the table below Fig 10 SW_ADC_1_r02 ADC Read Registers page When all registers have been read it is possible to save the data t...

Страница 17: ...age allows downloading configuration data to the device registers Fig 11 SW_ADC_1_r02 ADC Load Registers page It is not necessary to have a file that has the whole set of registers listed The only res...

Страница 18: ...ics are located in the Nyquist zone Enter your analog and sampling frequencies in field Indicate the number of samples to be acquired as well as the fixed parameter for the coherency calculation Fs in...

Страница 19: ...OS or LVDS DDR field press the INITIALIZATION button It will initialized the HSDC EXTMOD board FPGA is ready red LED is flashing on and off PLL embedded is locked green LED is on indicate whether Fin...

Страница 20: ...BFS dBc dBc dBFS dBc dBFS dBc dBc dBc dBc dBc dBc ADC1410S test ADC0 5 00 122 88 0 96 11 28 69 79 69 67 70 75 84 62 85 58 85 27 104 62 100 12 103 67 86 57 112 78 Note that ADC0 and ADC1 refer to the a...

Страница 21: ...uick start Rev 06 2 July 2012 21 of 27 3 2 5 2 Reorganized signal The reorganized signal displays the reconstructed sine wave from coherency calculation corresponding to 1 period of the input signal F...

Страница 22: ...nstructed signal The unreconstructed signal displays the unreconstructed sine wave corresponding to the whole number of period being acquired following the coherency rule Fig 16 SW_ADC_1_r02 Acquisiti...

Страница 23: ...2012 23 of 27 3 2 5 4 Histogram The histogram graph shows the distribution of output codes This graph shows which code is present and if there is any missing code in the conversion range Fig 17 SW_ADC...

Страница 24: ...fo page This page will give practical information related to software and hardware settings Fig 18 SW_ADC_1_r02 Info page The information visible on this page are board serial number HSDC software rel...

Страница 25: ...n such that it follows the equation above To do this iterative calculation one has to decide whether Fin or Fs is fixed To illustrate this process let s consider our current example with Fin 5 MHz Fs...

Страница 26: ...chnology Quick start ADC1410S ADC1210S ADC1010S series Quick start IDT 2012 All rights reserved Quick start Rev 06 2 July 2012 26 of 27 5 Notes For more information or sales office addresses please vi...

Страница 27: ...ut signals IN CLK 6 1 6 Output signals D0 to D13 OTR DAV 7 1 7 SPI Mode 7 1 8 SPI program 8 2 HSDC extension module acquisition board 9 2 1 HSDC extension module hardware initialization 10 2 2 HSDC ex...

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