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IDT 9FGV1006 Скачать руководство пользователя страница 8

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©2017 Integrated Device Technology, Inc.

October 20, 2017

9FGV1006 Register Descriptions and Programming Guide

Block Diagram

Figure 3. 9FGV1006 Block Diagram

Equations

:

FVCO = FCRYSTAL × Doubler × (Fractional Feedback Divider × 2)(see registers 0x10–0x19).
FOUT0 = FOUT1 = FVCO / Integer Divider (see registers 0x21 and 0x22).
Doubler is ×2 when enabled and ×1 when disabled.
The total feedback divider value is the fractional counter settings with an additional ×2.

Limits

:

FCRYSTAL: 10MHz–40MHz
FVCO: 2300MHz–2600MHz
Integer Output Divider: 8–4095
Feedback Divider: 12–255

Fractional Output Divider Configuration

The Fractional feedback divider (FFD) is composed of an 8-bit integer portion (address 0x12) and a 16-bit fractional portion (addresses
0x13 and 0x14).

FFD value P = INT(P) + FRAC(P) = FVCO / FPFD (1)
FFD Integer [7..0] = DEC2HEX(INT(P)) (2)

The FFD divides the VCO frequency FVCO down to the phase-frequency detector frequency FPFD. Note the additional divide by 2, so
F

PFD

= F

VCO

/ (2 × P).

Convert FRAC(P) to hex with Eq.2 where ROUND2INT means to round to the nearest integer. The round-off error of P in ppm is the
output frequency error in ppm.

FFD fraction [15..0] = DEC2HEX(ROUND2INT(216×FRAC(P))) (3)

Example

: Assume a 25MHz crystal, 122.88MHz output clocks and the VCO frequency is 20 × 122.88MHz = 2457.6MHz.

The phase frequency detector frequency F

PFD

= 2 × 25MHz = 50MHz and the FFD value is 2457.6 / 2 / 50 = 24.576.

The integer portion is 24, so address 0x12 will be 18-hex. The fractional portion is 0.576.

FFD Fraction [15..0] = DEC2HEX(ROUND2INT(216×0.576) = DEC2HEX(ROUND2INT(37748.736)) = DEC2HEX(37749) = 93 75.

Address 0x13 = 93-hex and address 0x14 = 75-hex.

There is a small error from the rounding. The actual FFD value is 24 + 37749 / 216 = 24.576004028. The rounding error is
24.576004028 / 24.576 - 1 = 0.16ppm.

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Содержание 9FGV1006

Страница 1: ... mode Using I2C commands the configuration can be changed and there are also commands to reload a configuration from a different OTP bank Figure 1 Register Maps User Configuration Selection At power up the voltage at REF0_SEL_I2CB pin 23 is latched by the part and used to select the state of SEL0 SCL and SEL1 SDA pins Table 1 When a weak pull up 10kΩ is placed on REF0_SEL_I2C the SEL0 SCL and SEL1...

Страница 2: ...and write block transfers can be stopped after any complete byte transfer During a write operation data will not be moved into the registers until the STOP signal is received at which point all data received in the block write will be written simultaneously in the registers For full electrical I2C compliance it is recommended to use external pull up resistors for SDATA and SCLK The internal pull u...

Страница 3: ...x03 0x04 0x05 OUT1 output settings 0x06 0x07 0x08 Reserved 0x09 0x0A 0x0B OUT0 output settings 0x0C 0x0D 0x0E Crystal oscillator settings 0x0F 0x10 Fractional feedback divider FFD spread spectrum settings 0x11 0x12 FFD integer value 0x13 FFD fractional value 0x14 0x15 FFD spread spectrum settings 0x16 0x17 FFD miscellaneous 0x18 0x19 0x1A PLL miscellaneous 0x1B 0x1C PLL loop filter settings 0x1D 0...

Страница 4: ...able REF outputs 0x REF0 disabled unused 1x REF0 enabled 5 0 Reserved 4 0 Behavior when REF is unused 0 Logic 0 1 High impedance tri state 3 2 11 REF outputs power supply voltage 00 01 1 8V 10 2 5V 11 3 3V 1 0 11 Reserved 02 0x02 7 0 8F hex Reserved 03 0x03 7 0 01 hex Reserved 04 0x04 7 0 44 hex Reserved 05 0x05 7 1 Enable OUT1 0 disabled unused 1 enabled 6 4 000 OUT1 configuration 000 LP HCSL Low...

Страница 5: ... 6 4 000 OUT0 configuration 000 LP HCSL Low power HCSL 001 CMOS1 Single ended CMOS on true output pin 011 LVDS 100 CMOS2 Single ended CMOS on complementary output pin 101 CMOSD Differential CMOS 111 CMOSP Two single ended CMOS outputs in phase 010 and 110 are not used 3 2 11 OUT0 power supply voltage 00 01 1 8V 10 2 5V 11 3 3V 1 0 11 Reserved 12 0x0C 7 0 Reserved 6 0 Behavior when OUT0 is unused 0...

Страница 6: ...rum configuration 17 0x11 7 0 00 hex FFD spread spectrum period bits 7 0 18 0x12 7 0 0C hex FFD integer value See section Fractional Output Divider Configuration for fractional feedback divider configuration 19 0x13 7 0 80 hex FFD fractional value bits 15 8 20 0x14 7 0 00 hex FFD fractional value bits 7 0 21 0x15 7 0 00 hex FFD spread spectrum step bits 15 8 22 0x16 7 0 00 hex FFD spread spectrum ...

Страница 7: ... band value in bits 5 0 5 0 100000 VCO band value See bit 6 27 0x1B 7 1 Enable VCO 0 VCO disabled 1 VCO enabled 6 1 Enable charge pump 0 CP disabled 1 CP enabled 5 1 Enable PLL bias 0 PLL bias disabled 1 PLL bias enabled 4 1 Bypass 3rd pole in loop filter 0 use 3rd pole 1 3rd pole bypassed 3 0 1100 Reserved 28 0x1C 7 4 1010 Loop filter R zero value 3 0 1111 Reserved 29 0x1D 7 0 00 hex Reserved 30 ...

Страница 8: ...O FPFD 1 FFD Integer 7 0 DEC2HEX INT P 2 The FFD divides the VCO frequency FVCO down to the phase frequency detector frequency FPFD Note the additional divide by 2 so FPFD FVCO 2 P Convert FRAC P to hex with Eq 2 where ROUND2INT means to round to the nearest integer The round off error of P in ppm is the output frequency error in ppm FFD fraction 15 0 DEC2HEX ROUND2INT 216 FRAC P 3 Example Assume ...

Страница 9: ...200 FVCO 2 FPFD 5 Note that the SS value is the peak to peak value so with 1 0 center spread the SS value is 2 0 Consider one cycle of down spread triangular modulation the FFD value is ramped down linearly from the P value followed by a linear ramp back up to the value of P The modulated value of the FFD is always smaller than or equal to the value of P Table 4 Spread Spectrum Variables in the FF...

Страница 10: ... modulation rate The crystal is 25MHz and the doubler is enabled so FPFD 25MHz 2 50MHz FFD value P FVCO 2 FPFD 2500 2 50 25 FOD integer 7 0 DEC2HEX 25 19 hex FOD fraction 15 0 DEC2HEX ROUND2INT 216 0 DEC2HEX ROUND2INT 0 00 00 hex Period decimal FPFD 2 FSS 50 2 0 0315 793 6508 Period 11 0 DEC2HEX ROUND2INT Period decimal 2 DEC2HEX 397 1 8D hex Step decimal SS 100 P Period 0 5 100 25 793 6508 1 575 ...

Страница 11: ... Ci1 Cs1 Ce1 Capacitance on pin XOUT or X2 Cx2 Ci2 Cs2 Ce2 Total Crystal Load Capacitance CL Cx1 Cx2 Cx1 Cx2 For optimum balance and oscillator gain it is recommended to design Cx1 Cx2 In that case CL Cx1 2 Cx2 2 The capacitance per pin X1 or X2 is Cap pF 7 98 0 442 Bits 4 0 7 072 Bit 5 This includes an estimated Cs1 Cs2 1 5pF When designing Cx1 Cx2 the formula for CL is CL pF 3 99 0 221 Bits 4 0 ...

Страница 12: ...rd parties IDT s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea sonably expected to significantly affect the health or safety of users Anyone using an IDT product in such a manner does so at their own risk absent an express written agreement by I...

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