IDT 89HPES16T4AG2, Руководство пользователя

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IDT Clocking, Reset and Initialization
PES16T4AG2 User Manual 2 - 2 May 23, 2013
Notes
Reset
The PES16T4AG2 defines four Conventional Reset categories: Fundamental reset, Hot Reset,
Upstream Secondary Bus Hot-Reset, and Downstream Secondary Bus Hot-Reset.
– A Fundamental Reset causes all logic in the PES16T4AG2 to be returned to an initial state.
– A Hot Reset causes all logic in the PES16T4AG2 to be returned to an initial state, but does not
cause the state of register fields denoted as “sticky” to be modified.
– An Upstream Secondary Bus Reset causes all devices on the virtual PCI bus to be hot reset
except the upstream port (i.e., upstream PCI to PCI bridge).
– A Downstream Secondary Bus Reset causes a hot reset to be propagated on the corresponding
external secondary bus link.
There are two sub-categories of Fundamental Reset: Cold reset and Warm reset. A Cold Reset occurs
following the PES16T4AG2 being powered on and assertion of PERSTN. A Warm Reset is a Fundamental
Reset that occurs without removal of power.
Fundamental Reset
A Fundamental Reset may be initiated by any of the following conditions:
– A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input
pin.
– A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power
is on.
– A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch
Control (SWCTL) register.
When configured to operate in normal mode, the following reset sequence is executed.
1. Wait for the Fundamental Reset condition to clear (e.g., negation of PERSTN). Note that PERSTN
must be asserted for at least 100ms (Tpvperl) after the PES16T4AG2 power supplies are stable,
and 100µs (Tperst-clk) after the reference clock input is stable.
2. On negation of PERSTN, sample the boot configuration signals listed in Table 2.1. If PERSTN was
not asserted, use the previously sampled boot configuration signal values (e.g., when a Funda-
mental Reset is the result of setting the Fundamental Reset (FRST) bit in the Switch Control
(SWCTL) register).
3. Examine the state of the sampled SWMODE[2:0] signals to determine the switch operating mode.
4. The PLL and SerDes are initialized (i.e., PLL/CDR reset and lock).
5. Link training begins. While link training is in progress, proceed to step 6.
6. If the Reset Halt (RSTHALT) pin is asserted, the RSTHALT bit in the SWSTS register is set.
7. If the switch operating mode is not a test mode, then the reset signal to the PCI Express stacks and
associated logic is negated but they are held in a quasi-reset state in which the following actions
occur.
• All links enter an active link training state within 20ms of the clearing of the Fundamental Reset
condition.
• Within 100ms of the clearing of the Fundamental Reset condition, all of the stacks are able to
process configuration transactions and respond to these transactions with a configuration
request retry status completion. All other transactions are ignored.
8. The master SMBus operating frequency is determined.
The state of the MSMBSMODE signal is examined. If it is asserted, then the master SMBus is ini-