IDT 89EBPES16T4G2, Руководство пользователя

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IDT Installation of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 2 - 6 October 3, 2007
Notes
SMBus Interfaces
The System Management Bus (SMBus) is a two-wire interface through which various system compo-
nent chips can communicate. It is based on the principles of operation of I
2
C. Implementation of the SMBus
signals in the PCI Express connector is optional and may not be present on the host system. The SMBus
interface consists of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins.
The PES16T4G2 contains two SMBus interfaces: a slave SMBus interface and a master SMBus inter-
face. The slave SMBus interface allows a SMBus Master device full access to all software-visible registers.
The Master SMBus interface provides connection to the external serial EEPROM used for initialization and
the I/O expanders used for hot-plug signals.
SMBus Slave Interface
On the PES16T4G2 board, the slave SMBus interface is accessible through the PCI Express edge
connector as well as a 4-pin header as described in Table 2.9.
Note: The SMBus signals to the PCI Express edge connector is disabled by default. To enable
them, place 0-ohm resistors at locations R160 and R161.
.
A fixed slave SMBus address ( 0b1100_000) specified by the SSMBADDR[5,3:1] pins is used.
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
Initiation of any SMBus transaction other than those listed above produces undefined results. See the
SMBus 2.0 specification for a detailed description of the following transactions:
– Byte and Word Write/Read
– Block Write/Read
Slave SMBus Interface Connector J8
Pin Signal
1 N/C
2 SCL
3 GND
4 SDA
Table 2.9 Slave SMBus Interface Connector
Slave Interface Address Configuration
Address Bit Signal
1 SSMBUSADDR[1]
2 SSMBUSADDR[2]
3 SSMBUSADDR[3]
4 0
5 SSMBUSADDR[5]
6 1
7 1
Table 2.10 SMBus Slave Interface Address Configuration