IDT 89EBPES16T4G2, Руководство пользователя

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IDT Installation of the EB16T4G2 Eval Board
EB16T4G2 Eval Board Manual 2 - 4 October 3, 2007
Notes
Fundamental Reset
There are two types of Fundamental Resets which may occur on the EB16T4G2 evaluation board:
– Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI
Express Reset (PERSTN) input pin of the PES16T4G2.
– Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be
initiated by two methods:
• Pressing a push-button switch (S1) located on EB16T4G2 board
• The host system board IO Controller Hub asserting PERST# signal, which propagates through
the PCIe upstream edge connector of the EB16T4G2. Note that one can bypass the onboard
voltage monitor (TLC7733D) by moving the shunt from pin 1-2 to pin 2-3 (default) on W4.
Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset
(PERSTN) input of the PES16T4G2 while power is on.
Downstream Reset
The PES16T4G2 provides a a choice of either a software-controlled reset for each downstream port
through GPIO pins or a fundamental reset through PERST#. Selection is made by jumpers described in
Table 2.6.
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 2.7 is sampled by the PES16T4G2
during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential
parameters for switch operation and is set using DIP switches S7 and S8 as defined in Table 2.8.
Port # Jumper Selection
2 W19 [1-2] Software controlled reset through GPIO0
[2-3] Fundamental reset PERST# (default)
4 W17 [1-2] Software controlled reset through GPIO1
[2-3] Fundamental reset PERST# (default)
6 W18 [1-2] Software controlled reset through GPIO11
[2-3] Fundamental reset PERST# (default)
Table 2.6 Downstream Reset Selection
Signal Description
CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream
ports are using the same clock source as that provided to downstream devices. This pin is
used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers
for downstream ports. The value may be overridden by modifying the SCLK bit in the down-
stream port’s PCIELSTS register.
Default: 0x1
CCLKUS Common Clock Upstream. The assertion of this pin indicates that the upstream port is
using the same clock source as the upstream device. This pin is used as the initial value of
the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value
may be overridden by modifying the SCLK bit in the P0_PCIELSTS register.
Default: 0x1
MSMBSMODE Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 kHz. Default: 0x0
Table 2.7 Boot Configuration Vector Signals (Part 1 of 2)