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©2018 Integrated Device Technology, Inc.
August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Fractional Output Dividers and Spread Spectrum
The output dividers are composed of a 12 bit integer portion, ODx_intdiv[11:0] and a 24 bit fractional portion, ODx_frcdiv[23:0]. “x” is the
output number.
ODx = INT(ODx) + FRAC(ODx) = FVCO / 2 / OUTx (1)
Convert FRAC(ODx) to hex with Eq.2 where ROUND2INT means to round to the nearest integer. The round-off error of ODx in ppm is the
output frequency error in ppm.
ODx_frcdiv[23:0] = DEC2HEX(ROUND2INT[224 * FRAC(ODx)]) (2)
Example
: The VCO is 2500MHz and the output needs to be 40MHz.
The output divider value needs to be 2500 / 2 / 40 = 31.25.
Then INT(ODx) = 31 and FRAC(ODx) = 0.25 that gives:
2
24
× FRAC(ODx) = 2
24
× 0.25 = 4194304
ROUND2INT(4194304) = 4194304
ODx_frcdiv[23:0] = DEC2HEX(4194304) = 40 00 00
Spread spectrum capability is contained within the Fractional-N output dividers associated with each output clock. When applied, triangle
wave modulation of any spread spectrum amount, SS%AMT, from ±0.25% to ±2.5% center spread and - 0.5% to -5% down spread
between 30 and 63kHz may be generated, independent of the output clock frequency. Five variables define spread spectrum in FODx
(see
).
Table 42. RAM1 – 0x1F: RC Control Register
Bits
Default Value
Name
Function
D7
0
p3byp
Enable or disable bypass 3rd pole filter
D6
0
cnf_p3[5:0]
3rd pole RC configuration. Following values are programmable with bits D1 through D6:
D3D2D1 = 001
→
2kOhm D6D5D4 = 001
→
1.8pF
D3D2D1 = 010
→
8kOhm D6D5D4 = 011
→
3.6pF
D3D2D1 = 011
→
1.6kOhm D6D5D4 = 111
→
5.4pF
D3D2D1 = 100
→
1kOhm.
D3D2D1 = 101
→
7kOhm.
D3D2D1 = 110
→
5.3kOhm.
D3D2D1 = 111
→
1.45kOhm.
D5
1
D4
1
D3
0
D2
0
D1
1
D0
0
cnf_pfddly
Phase Frequency Detector delay configuration bit
