(8042) Port 2, bit 3 (P23). P23 is set high from reset. Setting P23
low starts the watchdog timer timeout of 1.2 seconds (nominal).
Before the end of the timeout , P23 must be toggled high then low to
restart the timeout. If P23 is left low until the end of the timeout, the
watchdog timer issues a hardware reset to the processor board. The
timer should be refreshed by the software every 1.0 seconds to
prevent a timeout.
A set of watchdog timer software is available from Technical Sup-
port. The software includes sample C code which can be embedded
in a user program and demo software to demonstrate and test the
watchdog timer.
SPECIFICATIONS
TECHNICAL REFERENCE
1-11
Содержание SB586TCP/166
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