NOVA-7895 Socket 370 Celeron
TM
& Pentium III
®
Multimedia & Dual Ethernet ,IEEE1394, Embedded Board
47
4.8 Advanced Chipset Features
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
access to system memory resources, such as DRAM and the external
cache. It also coordinates communications between the conventional
ISA bus and the PCI bus. It must be stated that these items should
never need to be altered. The default settings have been chosen
because they provide the best operating conditions for your system.
Advanced DRAM Control 1 / 2 Settings
The first chipset settings deal with CPU access to dynamic random
access memory (DRAM). The default timings have been carefully chosen
and should only be altered if data is being lost. Such a scenario might
well occur if your system had mixed speed DRAM chips installed so that
greater delays may be required to preserve the integrity of the data held
in the slower memory chips.
NOVA-7895 Socket 370 Celeron
TM
& Pentium III
®
Multimedia & Dual Ethernet ,IEEE1394, Embedded Board
48
Auto Configuration
This item will automatically configure the chipset timing. You may select 'manual'
to set up following gray items by your specific need.
The choice: Manual, Auto, 100MHZ, 133MHZ.
SDRAM RAS Active Time
This item defines SDRAM ACT to PRE command period.
The Choice: 6T, 7T, 5T, 4T.
SDRAM RAS Precharge Time
This item defines SDRAM PRE to ACT command period.
The Choice: 3T, 2T, 4T, Reserved.
RAS to CAS Delay
This item defines SDRAM ACT to Read/Write command period.
The choice: 3T, 2T, 4T, Reserved.
Dram Background Command
This item is lead-off time control for DRAM background command. When 'Delay
1T' is selected, background commands are issued 1 clock behind memory
address (MA). When 'Normal' is selected, background command and MA are
issued at the same time.
The choice: Delay 1T, Normal.
LD-Off Dram RD/WR Cycles
The item is lead-off time control for DRAM Read/Write Cycles. When select
'Delay 1T' , memory read/write command is issued 1 clock behind memory
address (MA) been issued. When select 'Normal', read/write command and MA
are issued at the same time.
The choice: Delay 1T, Normal.
Write Recovery Time
