NOVA-3710/3710SV Socket 370 Celeron
TM
& Pentium III
®
Multimedia & Dual VGA , Ethernet Embedded Board
52
Graphic Window WR Combin
Use this item to enable or disable CPU support for WR Combin.
The Choice : Enable , Disable .
Concurrent Function ( MEM )
This item is CPU & PCI Masters Concurrently Access Memory Function. Select
enabled allows CPU access memory cycles and PCI masters access memory
cycles concurrently issued onto host bus and PCI bus, respectively, and then the
memory access cycles will be rearranged by SIS630S to memory sequentially.
The choice: Enabled, Disabled
Concurrent Function ( PCI )
This item is CPU & PCI Masters Concurrently Access PCI Bus Function. Select
enabled allows CPU access PCI bus cycle and PCI masters access memory
cycles concurrently issued onto host bus and PCI bus, respectively.
The choice: Enabled, Disabled.
CPU Pipeline Control
When enabled this item, only one pending cycle is allowed at one time.
When disabled, there might be more than two pending cycles at one time
depends on the CPU behavior.
The choice: Enabled, Disabled.
PCI Delay Transaction
If the chipset has an embedded 32-bit write buffer to support delay
transaction cycles, you can enable this item to provide compliance with
PCI Ver.2.1 specifications. We recommend that you leave this item at the
default value.
The choice : Enable, Disable.
Power-Supply Type
Содержание NOVA-3710
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