NOVA-3710/3710SV Socket 370 Celeron
TM
& Pentium III
®
Multimedia & Dual VGA , Ethernet Embedded Board
50
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing.
The Choice: 2, 3 , SPD
SDRCLK Control
This item controls the phase of SDRCLK that lags behind SDCLK.
The choice: Enabled, Disabled.
SDWCLK Control CS#/CKE
This item controls the phase of SDWCLK used for chip set select signals pin that
lags ahead SDCLK.
The choice: Enabled, Disabled.
SDWCLK Control MA/SRAS
This item controls the phase of SDWCLK used for MA/ SRAS signals that lags
ahead SDCLK.
The choice: +5.0ns~-2.5ns (Default 0.0ns)
SDWCLK Control DQM/MD
This item controls the phase of SDWCLK used for DQM/MD signals that lags
ahead SDCLK.
The choice: +5.0ns~-2.5ns (Default 0.0ns)
EGMRCLK Control
This item controls the phase of EGMRCLK that lags behind SDCLK.
The choice: -1.0ns~+6.5ns (Default 0.0ns)
Содержание NOVA-3710
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