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Appendix A Watchdog Timer
Watchdog Timer is provided to ensure that standalone systems can always
recover from catastrophic conditions that caused the CPU to crash. This condition
may have occurred by external EMI or a software bug. When the CPU stops
working correctly, hardware on the board will either perform a hardware reset
(cold boot) or a non-maskable interrupt (NMI) to bring the system back to a
known state.
Watchdog Timer is controlled by two I/O ports.
443 (hex) Read
Enable the refresh the Watchdog Timer.
843 (hex) Read
Disable the Watchdog Timer.
To enable Watchdog Timer, a read from I/O port 443H must be performed. This
will enable and activate the countdown timer which will eventually time out and
either reset the CPU or cause an NMI depending on the setting of JP4. To ensure
that this reset condition does not occur, the Watchdog Timer must be periodically
refreshed by reading the same I/O port 433H. This must be done within the time
out period that is selected by jumper JP3.
A tolerance of at least 30% must be maintained to avoid unknown routines within
the operating system (DOS), such as disk I/O that can be very time consuming.
Therefore if the time out period has been set to 10 seconds, the I/O port 443H
must be read within 7 seconds.
Note: Disable Watchdog Timer when exiting a program, otherwise the system will
reset.
