5.1.4
J2 Description:
Address bus (output): A0 ~ A6, A7
Data Bus (tri-state, bi-direction): D0 to D7
INT4: let this pin OPEN for no interrupt applications
/CS, /RD, /WR: These 3 signals will synchronous to CLOCKA (in
J1.3) & asynchronous to ARDY (J1.4)
The CS\ will be active if program input/output from I/O address 0
to 0xff.
The pin_15 & pin_17 are reserved by 7188XC & 7521 series;
user must left these two pins N/C for 7188XC & 7521 series.
I/O Expansion Bus for 7188X/7188E User’s Manual, Jan/2005 v1.5, 7PH-000-15---24