
4-3 PLL CIRCUITS
4-3-1 GENERAL (MAIN UNIT)
A PLL circuit provides stable oscillation of the transmit fre-
quency and the receive local frequency. The PLL circuit
compares the phase of the divided VCO frequency to the
reference frequency. The PLL output frequency is controlled
by a crystal oscillator and the divided ratio of the program-
mable divider.
4-3-2 VHF LOOP (VCO BOARD)
The generated signal at the V-VCO (Q3, D1, D2) enters the
PLL IC (MAIN unit; IC1, pin 8) via the buffer amplifiers (Q6,
Q8) and VCO switch (D50).
The applied signal is divided at the prescaler and program-
mable counter section by the N-data ratio from the main CPU
(MAIN unit: IC505). The divided signal is detected on phase
at the phase detector using the reference frequency and out-
put from pin 15. The output signal is passed through the loop
fi lter and is then applied to the V-VCO circuit.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
4-3-3 UHF LOOP (VCO BOARD)
The generated signal at the U-VCO (Q101, D100, D101)
enters the PLL IC (MAIN unit; IC2, pin 8) via the buffer
amplifiers (Q50, Q102) and VCO switch (D51).
The applied signal is divided at the prescaler and program-
mable counter section by the N-data ratio from the main CPU
(MAIN unit: IC505). The divided signal is detected on phase
at the phase detector using the reference frequency and out-
put from pin 5. The output signal is passed through the loop
fi lter and is then applied to the U-VCO circuit.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
4-3-4 VCO CIRCUIT (VCO BOARD )
The 1st LO circuit contains a separate V-VCO (Q3, D1, D2)
and U-VCO (Q101, D100, D101).
4 - 7
• 1ST LO CIRCUIT
Frequency range
VCO
1st
mixer
Lo
switch
118–174 MHz
V-VCO
Q23
D6
430–440 MHz (EXP)
440–450 MHz (USA)
U-VCO
Q35
D104
230–550 MHz
U-VCO
IC12 pin 3
D104
800–1000 MHz
U-VCO
IC12 pin 3
D105
Shift register
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X1
15.2 MHz
45.6 MHz 2nd LO signal
to the FM IF IC (IC8, pin 2)
1
Buffer
Buffer
Buffer
9
10
11
PLLCK
PLLDATA
PLLSTB1
to the 1st mixer circuit
to the transmitter circuit
D5
D6
15
8
IC1 MB15A02PFV1
Q3, D1, D2
VHF VCO
Q4
Buffer
Q2
×
3
Q7
D50
VCO
switch
LO switch
Q5
Q50
• VHF PLL CIRCUIT
Содержание ID-800H
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