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4 - 7
4-5 PORT ALLOCATIONS
4-5-1 CPU (LOGIC-1 UNIT; IC50)
Pin
number
Port
name
Description
29 MU/D
Input port for up/down signal from the
connected microphone.
32 NOIS
Input port for the noise signal from the
noise detector (MAIN unit; D195).
31 RSSI
Input port for the S-meter signal from
the demodulator IC (MAIN unit; IC191,
pin 12).
33 TONI
Input port for CTCSS signal from the
low-pass fi lter (MAIN unit, IC1461, pin
1).
42 TXD1
Output data signals to the USB con-
troller (IC550, pin 24).
43 RXD1
Input port for data signals from the
USB controller (IC550, pin 25) via the
(IC553).
53 SDA
I/O port for data signals from/to the
EEPROM (IC54, pin 5).
54 SCL
Outputs clock signal to the EEPROM
(IC54, pin 6).
61 BEEP Outputs beep audio signals.
71 RESET
Input port for reset signal form the re-
set IC (IC52, pin 1).
72 P2RSC
Outputs control signal to the mode
switch (MAIN unit; IC551, pin 5) via
the level converter (IC55).
73 P2STC
Outputs strobe signal to the 2nd PLL
IC (MAIN unit; IC550, pin 3) via the
level converter (IC55).
74 PDATC
Outputs the data signal to the 1st and
2nd PLL ICs (MAIN unit; IC400, pin 15,
IC550, pin 5) via the level converter
(IC55).
75 PSCKC
Outputs clock signal to the 1st and 2nd
PLL ICs (MAIN unit; IC400, pin 14,
IC550, pin 4) via the level converter
(IC55).
76 P1STC
Outputs strobe signal to the 1st PLL
IC (MAIN unit; IC400, pin 16) via the
level converter (IC55).
77 +5AC
Outputs control signal to the 5A
(Q1345) and D+5 (Q1347) regulators
via the level converter (IC55).
Low:
While the +5 and D+5 regu-
lators are activated.
78 W/NSC
Outputs control signal to the DV/FM
filter switches (MAIN unit; D192,
D193) via the level converter (IC55).
High:
While DV mode is selected.
79 ADSWC
Outputs control signal to the mode
switches (MAIN unit; IC1411, IC1670,
IC1673) via the level converter (IC55).
Low: While DV mode is selected.
80 TXLED
Outputs TX LED control signal.
High:
During transmit.
82 RXLED
Outputs RX LED control signal.
High: While receiving or squelch is
opened.
Pin
number
Port
name
Description
85 PCON
Outputs control signal to the TX power
controller (MAIN unit; Q1250).
86 ULCK
Input port for the PLL unlock signal.
High: The PLL circuit is unlocked.
87 MMUT
Outputs the microphone mute sig-
nal to the mute switch (MAIN unit;
Q1670).
Low:
While microphone audio is
muted.
93 SCAN
Outputs scan control signal to the
scan switch (Q400).
High:
While scanning.
94 TXS
O u t p u t s t h e T + 5 , T + 3 r e g u l a t o r
circuits (MAIN unit; Q1336, Q1342)
control signal.
High:
During transmit.
95 RXS
Outputs the R+5, R+3 regulator
circuits (MAIN unit; Q1337, Q1343)
control signal.
High:
During receive.
96 AMUT
Outputs the AF mute signal to the AF
mute switch (MAIN unit; Q1550).
Low:
W h i l e d i g i t a l c o d e / c a l l
sign/noise/tone squelch are
closed, the audio level is
set to minimum position or
transmitting.
102 RMUT
Outputs the SQL mute signal to the
AF switch (MAIN unit; IC1463, pin 2).
High:
While noise or tone squelch
is closed.
103 AFCSW
Outputs AFC switch (IC352, pin 5)
control signal.
105 DACK2
Outputs clock signal to the D/A con-
verter (IC57, pin 7).
106 DADAT2
Outputs the data signal to the D/A
converter (IC57, pin 6).
107 DACK1
Outputs clock signal to the D/A con-
verter (IC56, pin 7).
108 DADAT1
Outputs the data signal to the D/A
converter (IC56, pin 6).
128 FSTB
Outputs strobe signal to the FPGA IC
(IC200).
129 MSTRC
Outputs strobe signal to the liner
C O D E C I C ( I C 1 ) a n d F P G A I C
(IC200).
130 MDATC
Outputs the data signal to the liner
C O D E C I C ( I C 1 ) a n d F P G A I C
(IC200).
131 MCLKC
Outputs clock signal to the liner
C O D E C I C ( I C 1 ) a n d F P G A I C
(IC200).
132 MRESC
Outputs reset signal to the liner
C O D E C I C ( I C 1 ) a n d F P G A I C
(IC200).