Icom ID-1, Руководство по обслуживанию

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4 - 6
4-4-2 MAIN UNIT VOLTAGE LINE
Line Description
HV The voltage from a DC power supply.
VCC
The same voltage as the HV line which
is controlled by the power switching cir-
cuit (Q23, Q24). When the power switch is
pushed, the CPU outputs the "PWR" control
signal to the power switching circuit to turn
the circuit ON.
+9
Common 9 V converted from the HV line at
the +9 CTRL circuit (IC1330). The output
voltage is applied to the volume controller
(IC1550), etc.
+5
Common 5 V converted from the +9V line at
the 5 V regulator circuit (IC1331). The out-
put voltage is applied to the mode switches
(IC1462, IC1463), etc.
DM+5
Common 5 V converted from the +9V line at
the 5 V regulator circuit (IC830). The output
voltage is applied to the modulation ampli-
fi ers (IC831, IC832), etc.
T+9
Transmit 9 V controlled by the T+9 regula-
tor circuit (Q1333, Q1334, D1331) using the
"TXS" signal from the CPU (LOGIC-1 unit;
IC50, pin 94). The output voltage is applied
to the APC amplifi er (IC1250), etc.
T+5
Transmit 5 V controlled by the T+5 regula-
tor circuit (Q1336, D1332, D1333) using the
"TXS" signal from the CPU (LOGIC-1 unit;
IC50, pin 94). The output voltage is applied
to the RF amplifi er (IC1021), etc.
R+5
Receive 5 V controlled by the R+5 regulator
circuit (Q1337) using the "RXS" signal from
the CPU (LOGIC-1 unit; IC50, pin 95). The
output voltage is applied to the RF amplifi er
(Q2) and 1st mixer (IC71), etc.
T+3
Transmit 3 V controlled by the T+3 regulator
circuit (Q1342) using the "TXS" signal from
the CPU (LOGIC-1 unit; IC50, pin 94). The
output voltage is applied to the 1st mixer
(IC960), etc.
R+3
Receive 3 V controlled by the R+3 regulator
circuit (Q1343) using the "RXS" signal from
the CPU (LOGIC-1 unit; IC50, pin 95). The
output voltage is applied to the RF amplifi er
(Q1), etc.
4-4 POWER SUPPLY CIRCUITS
4-4-1 LOGIC-1 UNIT VOLTAGE LINE
Line Description
5V
Common 5 V controlled by the +5 V regula-
tor circuit (Q50 and Q51) using the “PWRS”
signal from the CPU (IC50, pins 101).
3.3V
Common 3.3 V converted from the 5V line
by the 3.3V regulator circuit (IC502).
3.2V
Common 3.2 V converted from the 5 V line
by the 3.2V regulator circuit (IC4).
signal from the 1st VCO (Q471, Q472, D471) is applied to
the buffer amplifi ers (Q473, Q474) and is then applied to the
PLL IC (IC400, pin 6).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc.
The applied signal is divided at the prescaler and program-
mable counter section by the N-data ratio from the CPU
(LOGIC-1 unit; IC50). The divided signal is detected on
phase at the phase detector using the reference frequency
and output from pin 4. The output signal is passed through
the loop filter and is then applied to the 1st VCO circuit.
The oscillated signal at the 1st VCO is buffer amplified at
Q473 and then passed through the low-pass (L474, L475,
C488–C492) and high-pass (L47–L477, C493–C497) filters.
The filtered signal is applied to the buffer amplifier (Q710)
and then applied to the T/R switch (D710, D711).
The receive 1st LO signal from the T/R switch (D711) is
applied to the 1st mixer circuit (IC71).
The transmit signal from the T/R switch (D710) is applied to
the 1st mixer circuit (IC960).
A portion of the signal from the buffer amplifier (Q473) is
fed back to the PLL IC (IC400, pin 6) via the buffer amplifier
(Q474) as the comparison signal.
4-3-3 2ND PLL CIRCUIT (MAIN UNIT)
The 2nd PLL circuit oscillates the 2nd LO frequency, and the
signal is applied to the 2nd mixer circuits.
The signal oscillated at the 2nd VCO circuit (Q631, D630) is
amplifi ed at the buffer amplifi ers (Q632, Q633), then applied
to the PLL IC (IC550, pins 2, 19). The applied signal is
divided at the prescaler and programmable counter section
by the N-data ratio from the CPU (LOGIC-1 unit; IC50). The
divided signal is detected on phase at the phase detector
using the reference frequency and output from pins 8, 13
(IC550).
While operating in DV/DD mode, the detected signal from
pin 13 (IC550) is passed through the loop filter (R555–R557,
C564, C567) and then applied to the 2nd VCO circuit via the
mode switch (IC551, pins 1, 7).
While operating in FM mode, the detected signal from pin 8
(IC550) is passed through the loop filter (R559–R561, C571,
C574) and then applied to the 2nd VCO circuit via the mode
switch (IC551, pins 1, 6).
The oscillated signal at the 2nd VCO is amplified at the buf-
fer amplifiers (Q632 Q771), and is then applied to the T/R
switch (D770, D771).
The receive 2nd LO signal from the T/R switch (D771) is
applied to the 2nd mixer circuit (Q131).
The transmit signal from the T/R switch (D770) is applied to
the 2nd LO amplifier (Q890).
A portion of the signal from the buffer amplifier (Q632) is fed
back to the PLL IC (IC550, pins 2, 19) via the buffer ampli-
fier (Q633) and low-pass filter (L631, C653, C654) as the
comparison signal.