4 - 5
4-3-3 EAR PHONE ANTENNA CIRCUIT
(LOGIC AND RF UNITS)
When switching to the ear phone antenna while WFM band
receiving, the received RF signal passes through the exter-
nal speaker jack (LOGIC unit; J2). The signal is applied to the
D101’s anode side (RF unit), and is then applied to the RF
circuit.
4-3-4 RESET CIRCUIT (LOGIC UNIT)
When power switch is ON, +3CPU signal from the +3.2 reg-
ulator (IC103) is applied to the reset IC (IC3, pin 2). The IC
outputs reset signal via the “RESET” line, and the signal is
applied to the CPU (IC1, pin 19) to reset it.
4-3-5 LCD BACK LIGHT CIRCUIT (LOGIC UNIT)
When the LCD back lights ON, the LCD back light control sig-
nal becomes high, and is output from the CPU (IC1, pin 69)
as “LIGHT” signal. The signal is applied to the light swtich
(Q5), and is then applied to the LCD light LED (EP3).
LINE
HV
VCC
VP
+3CPU
+3V
+3S
R3V
DESCRIPTION
The voltage from the external power supply or
attached battery.
The same voltage as the “HV” line (external
power supply or battery pack).
Common 14 V converted from the clock signal
(LOGIC unit; IC1, pin 40) by the DC-DC conver-
tors (LOGIC unit; IC100, D100–D103). The out-
put voltage is applied to the PLL circuit, etc (RF
unit).
Common 3 V converted from the “VCC” line by
the +3.2 regulator IC (LOGIC unit; IC103). The
output voltage is supplied to the CPU, reset IC
(LOGIC unit; IC3), EEPROM (LOGIC unit; IC2),
etc.
Common 3 V converted by the +3 controller
(LOGIC unit; Q103) using the “PCON” signal
from the CPU. The output voltage is supplied to
the PLL IC (RF unit; IC3), etc.
Common 3 V converted by the +3S controller
(LOGIC unit; Q101, Q102) using the “PCON”
and “+3SC” signals from the CPU. The output
voltage is supplied to the ripple filter (RF unit,
Q37), etc.
Common 3 V converted by the R3V controller
(LOGIC unit; Q104) using the “+3SC” signal from
the CPU. The output voltage is supplied to the
buffer amplifier (LOGIC unit, Q400), AM detector
(RF unit; Q4), etc.
4-4 POWER SUPPLY CIRCUITS
VOLTAGE LINE
