The phase difference is output from pin 5 as a pulse type
signal after being passed through the internal charge pump.
The output signal is applied to the VCO (Q19, D43) after
being converted into the DC voltage (lock voltage) at the
loop filter (R84, R102, R106, C180, C188, C202, C645,
C646).
• 1st PLL
-1st VCO 1 (Q28, D53)-
A portion of the VCO output signals from the buffer amplifi er
(IC12, pin 4) are applied to the PLL IC (IC10, pin 8) via the
buffer amplifier (Q39). The applied signals are divided at
the prescaler and programmable counter according to the
N-data “DAT1” from the expnader (IC7, pin 2) controlled by
the CPU (IC18). The divided signal is phase compared with
the reference frequency at the phase comparator.
The phase difference is output from pin 5 as a pulse type
signal after being passed through the internal charge pump.
The output signal is applied to the VCO (Q27, Q28, D52,
D53) after being converted into the DC voltage (lock voltage)
at the loop fi lter (Q35, Q36).
-1st VCO 2 (Q30, D54)-
A portion of the VCO output signals from the buffer amplifi er
(IC12, pin 4) are applied to the PLL IC (IC10, pin 8) via the
buffer amplifier (Q39). The applied signals are divided at
the prescaler and programmable counter according to the
N-data “DAT1” from the expnader (IC7, pin 2) controlled by
the CPU (IC18). The divided signal is phase compared with
the reference frequency at the phase comparator.
The phase difference is output from pin 5 as a pulse type
signal after being passed through the internal charge pump.
The output signal is applied to the VCO (Q27, Q28, D52,
D53) after being converted into the DC voltage (lock voltage)
at the loop fi lter (Q35, Q36).
• 2nd PLL
A portion of the VCO (Q47, D62, D63) output signals from
the buffer (Q50) are applied to the PLL IC (IC13, pin 11)
via the buffer (Q41). The applied signals are divided at
the prescaler and programmable counter according to the
N-data “DAT1” from the expnader (IC3, pin 2) controlled by
the CPU (IC18). The divided signal is phase compared with
the reference frequency from the reference amplifi er (Q31)
at the phase comparator.
The phase difference is output from pin 5 as a pulse type
signal after being passed through the internal charge pump.
The output signal is applied to the VCO (Q47, D62, D63)
after being converted into the DC voltage (lock voltage) at
the loop fi lter (R235, R238, C354, C355, C362).
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
4 - 5
DATA interface
Prescaler
Phase
detector
Loop
filter
Reference
counter
Programmable
counter
Charge
pump
Buffer
amp.
Buffer
amp.
to a mixer
VCO
Reference frequency signal
PLL strobe signal
PLL unlock detect signal
<THE CONCEPT OF PLL CIRCUITS>
PLL crock signal
PLL serial data (N-data)
PLL IC
4-3 DIGITAL MODE OPERATION WITH UT-122
†
A portion of the 450 kHz 3rd IF signal from IF IC (MAIN-A UNIT;
IC24, pin 13) is applied to the LOGIC UNIT via the IF amplifi er
(MAIN-A UNIT; Q76, Q77). The applied 3rd IF signal is passed
through the IF switch (LOGIC UNIT; IC2028, pins 1, 7) and buffer
amplifier (LOGIC UNIT; Q2023), then applied to the attached
UT-122 via J2017 (pin 11).
The applied 3rd IF signal is passed through the IF filter
(UT-122; FI1) to remove unwanted signals, and applied to
the A/D converter (UT-122; IC8, pin 3) to be converted into
the digital signal via BPF. The converted digital signal is
then applied to the DSP (Digital Signal Proccesor; IC7) and
demodulated. The demodulated signal is then applied to the
liner codec (UT-122; IC9) to be converted in to the analog
audio signals.
The converted audio signals are applied to the same AF
circuits as analog receiving from the AF switch (IC23, pin 7).
†
Optional product (DIGITAL UNIT for PCR2500; [USA-3])
