4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT (MAIN UNIT)
The PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL circuit
compares the phase of the divided VCO frequency with the
reference frequency. The PLL output frequency is controlled
by the divided ratio (N-data) of the programmable divider.
The PLL circuit contains the two RX VCOs (Q4, D4, D5,
D24, D26 for 154–174 MHz, Q20, D27–D30 for 136–
153.995 MHz) and one TX VCO (Q5, D6, D7, D25). The
oscillated signal is amplified at the buffer amplifiers (Q6, Q9)
and applied to the PLL IC (IC1, pin 6) after being passed
through the BPF (Q1, D1, D2, L2, L56, L57, L302, C12,
C15, C20, C22, C25–C28, C32).
Q1, D1 and D2 compose of a BPF switch which toggles the
filtering frequencies for TX and RX, controlled by “T5C” sig-
nal from the CPU (IC307 pin 16).
The applied signal is divided at the prescaler and program-
mable divider section by the N-data ratio from the CPU.
The divided signal is detected at the phase detector sec-
tion via divided ratio adjustment section using the reference
frequency passed through the reference divider and output
from pin 4 after being passed through the charge pump sec-
tion. The output signal is passed through the loop filter (R16,
R17, C17, C24, C29, C31) and is then applied to the VCO
circuits.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
4-3-2 VCO CIRCUITS
The VCO circuits contain separate two RX VCOs (Q4, D4,
D5, D24, D26 for 154–174 MHz, Q20, D27–D30 for 136–
153.995 MHz) and one TX VCO (Q5, D6, D7, D25). The
oscillated signal is amplified at the buffer amplifiers (Q6,
Q10) and is then applied to the TX/RX switch (D9, D10).
Then the receive 1st LO (RX) signal is applied to the 1st
mixer (IC14, L30, L31, L33), and the transmit (TX) signal is
applied to the YGR amplifier (Q11).
4 - 4
Loop
filter
PLST
SSO
SCK
4
Q20, D27–D30
RX VCO (136–153 MHz)
Q4, D4, D5, D24, D26
RX VCO (154–174 MHz)
TX VCO
Q5, D6, D7, D25
6
10
14
15
16
PLL control signals from CPU (IC307)
15.3 MHz reference signal
from reference frequency osciilator (X3)
IC1 LMX2352TM
• PLL CIRCUIT
Shift register
Prescaler
Phase
detector
Divide
ratio
adjustment
Charge
pump
Programmable
divider
Reference
divider
Buffer
Q6
Buffer
Q10
Buffer
Q9
to transmitter circuit
to 1st mixer circuit
D3
D4
LPF
LINE
DESCRIPTION
VCC
The voltage from the attached battery pack passed
through the power switch (Q309).
CPU5V
Common 5 V for the CPU (IC307) converted from the
VCC line at the CPU5V regulator (IC311).
+5V
Common 5 V line converted from the VCC line at the
+5V regulator (Q307, Q308).
T5V
5 V for the transmit circuits regulated from the +5V line
by the T5V switch (Q305).
The switch is controlled by the "T5C" signal from the
CPU (IC307, pin 16).
S5V
5 V for the power save line regulated from the +5V line
by the S5V switch (Q304).
The switch is controlled by the "S5C" signal from the
CPU (IC307, pin 27).
R5V
5 V for the receive circuits regulated from the +5V line
by the R5V switch (Q306).
The regulator is controlled by the "R5C" signal from
the CPU (IC307, pin 26).
4-4 POWER SUPPLY CIRCUITS
4-4-1 VOLTAGE LINES (MAIN UNIT)
LINE
DESCRIPTION
DVDD3.3V
3.3 V for the CPU (IC12; DSP UNIT), DSP IC (IC7)
and EEPROM (IC17) regulated from the +5V line by
the +3VC regulator (IC1).
CVDD1.5V
1.5 V for the DSP IC (IC7) converted from the +5V
line at the +1.5VA regulator (IC2).
+3VD
3.3 V for the A/D converter (IC8) and LINER CODEC
IC (IC9) from the +5V line at the +3VD regulator (IC3).
4-4-2 VOLTAGE LINES (DSP UNIT)
A portion of the signal from the buffer amplifier (Q6) is fed
back to the PLL IC (IC1, pin 6) via the buffer amplifier (Q9)
and the BPF (Q1, D1, D2, L2, L56, L57, L302, C12, C15,
C20, C22, C25 to C28, C32) as the comparison signal.
Содержание IC-F70DS
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