IBT Technologies IB710, Руководство пользователя

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BIOS SETUP
40 IB710 User’s Manual
Chipset Features Setup
This menu controls the configuration of the embedded board chipset.
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
Auto Configuration : Enabled Auto Detect DIMM/PCI Clk : Disabled
SDRAM RAS-to-CAS Delay : 3 Spread Spectrum : Disabled
SDRAM RAS Precharge Time
:
3 CPU Host Clock (CPU/PCI) : Default
SDRAM CAS Latency Timer
:
3 CPU Warning Temperature : 66
°
C/151
°
F
SDRAM Precharge Control
:
Disabled Current System Temp. : 40
°
C/104
°
F
DRAM Data Integrity Mode : Non-ECC Current CPU/Chip Temperature : 41
°
C/105
°
F
System BIOS Cacheable : Enabled Current CPU/Block Temp. : 41
°
C/105
°
F
Video BIOS Cacheable : Enabled CPU Fan Speed : 4440 RPM
Video RAM Cacheable : Enabled Chassis Fan Speed : 0 RPM
8 Bit I/O Recovery Time
:
3 VCCP
(V):
1.98 V VTT (V) : 1.50 V
16 Bit I/O Recovery Time
:
2 VCC3 (V) : 3.45 V + 5 V : 4.99 V
Memory Hole At 15MB-16MB : Disabled +12 V : 12.46 V
Passive Release : Enabled :
Delayed Transaction : Disabled
AGP Aperture Size (MB) : 64
ESC : Quit
á â à ß
: Select Item
F1 : Help PU/PD/+/- : Modify
F5 : Old Values (Shift) F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
Auto Configuration
This field predefines values for DRAM, cache timing according to CPU
type and system clock. When this field is enabled, the predefined items
will become read-only.
SDRAM RAS-to-CAS Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This field allows you to determine the timing of transition
from Row Address Stove (RAS) to Column Address Strobe (CAS).
SDRAM RAS Precharge Time
The precharge time is the number of cycles it takes for the RAS to
accumulate its charge before DRAM refresh. If insufficient time is
allowed, refresh may be incomplete and the DRAM may fail to retain
data.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer.
SDRAM Precharge Control
This field enables of enables the SDRAM Precharge Control.