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IBM Power Systems S822LC for High Performance Computing
Here are additional features that can augment the performance of the POWER8 processor:
Support for DDR4 memory through memory buffer chips that offload the memory support
from the POWER8 memory controller.
An L4 cache within the memory buffer chip that reduces the memory latency for local
access to memory behind the buffer chip; the operation of the L4 cache is not apparent to
applications running on the POWER8 processor. Up to 128 MB of L4 cache can be
available for each POWER8 processor.
Hardware transactional memory.
On-chip accelerators, including on-chip encryption, compression, and random number
generation accelerators.
CAPI, which allows accelerators that are plugged into a PCIe slot to access the processor
bus by using a low latency, high-speed protocol interface.
Adaptive power management.
Table 1-3 summarizes the technology characteristics of the POWER8 processor.
Table 1-3 Summary of POWER8 processor technology
Technology
8335-GTB POWER8 processor
Die size
659 mm
2
Fabrication technology
22 nm lithography
Copper interconnect
SOI
eDRAM
Maximum processor cores
12
Maximum execution threads core/chip
8/96
Maximum L2 cache core/chip
512 KB/6 MB
Maximum On-chip L3 cache core/chip
8 MB/96 MB
Maximum L4 cache per chip
128 MB
Maximum memory controllers
2
SMP design-point
16 sockets with POWER8 processors
Compatibility
Specific to the 8335-GTB
Содержание S822LC
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