IBM PS700, Технический обзор и введение

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IBM BladeCenter PS700, PS701, and PS702 Technical Overview and Introduction
2.2.4 Memory access
Each POWER7 processor chip has two DDR3 memory controllers, each with four memory
channels (enabling eight memory channels per POWER7 processor). Each channel operates
at 6.4 Gbps and can address up to 32 GB of memory. Thus, each POWER7 processor chip is
capable of addressing up to 256 GB of memory.
Figure 2-4 gives a simple overview of the POWER7 processor memory access structure.
Figure 2-4 Overview of POWER7 memory access structure
2.2.5 Flexible POWER7 processor packaging and offerings
POWER7 processors have the unique ability to optimize to various workload types. For
example, database workloads typically benefit from fast processors that handle high
transaction rates at high speeds. Web workloads typically benefit more from processors with
many threads that allow the breakdown of Web requests into many parts and handle them in
parallel. POWER7 processors have the unique ability to provide leadership performance in
either case.
POWER7 processor 4-core and 6-core offerings
The base design for the POWER7 processor is an 8-core processor with 32 MB of on-chip L3
cache (4 MB per core). However, the architecture allows for differing numbers of processor
cores to be active: 4-cores or 6-cores, as well as the full 8-core version.
The L3 cache associated with the implementation is dependant on the number of active
cores. For a 6-core version, this typically means that 6 x 4 MB (24 MB) of L3 cache is
available. Similarly, for a 4-core version, the L3 cache available is 16 MB.
Note: In certain POWER7 processor-based systems (including the PS700, PS701, and
PS702 blades) only one memory controller is active.
Advanced
Buffer
ASIC Chip
Memory
Controller
Memory
Controller
POWER7 processor chip
Dual integrated DDR3 memory controllers

High channel and DIMM utilization

Advanced energy management

RAS advances
Eight high-speed 6.4 GHz channels

New low-power differential signalling
New DDR3 buffer chip architecture

Larger capacity support (32 GB/core)

Energy management support

RAS enablement
DDR3 DRAMs
P7 Core P7 Core P7 Core P7 Core
P7 Core P7 Core P7 Core P7 Core