4405ch02 Architecture and technical overview.fm
Draft Document for Review May 28, 2009 1:59 pm
32
IBM Power 570 Technical Overview and Introduction
between the memory controller and the buffer is changed from a shared parallel interface to a
point-to-point serial interface (see Figure 2-5).
Figure 2-5 Fully buffered DIMMs architecture
The result of the fully buffered memory DIMMs implementation is an enhanced scalability and
throughput.
2.4.2 Memory placements rules
The minimum memory capacity for a 570 initial order is 2 GB when a 3.5 GHz, 4.2 GHz, or
4.7 GHz system is configured with two processor-cores. FC 5620, FC 5622, and FC 7380
processor cards support up to 12 fully buffered DIMM slots and DIMMs must be installed in
quads. Then the quads are organized as follows:
First quad includes J0A, J0B, J0C, and J0D memory slots
Second quad includes J1A, J1B, J1C, and J1D memory slots
Third quad includes J2A, J2B, J2C, and J2D memory slots
See Figure 2-6 on page 33
to locate any available quad.
DRAM
DRAM
DRAM
DRAM
Memory
buffer
chip
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Memory
buffer
chip
DRAM
DRAM
DRAM
DRAM
...
DRAM
DRAM
DRAM
DRAM
Memory
buffer
chip
DRAM
DRAM
DRAM
DRAM
Memory
controller
POWER6
chip
Common clock
source