Chapter 2. Architecture and technical overview
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Draft Document for Review May 28, 2009 1:59 pm
4405ch02 Architecture and technical overview.fm
To verify the processor characteristics on a system running at 4.2 GHz, use one of the
following commands:
lsattr -El proc
X
Where
X
is the number of the processor, for example, proc0 is the first processor in the
system. The output from the command is similar to the following output (
False
, as used in
this output, signifies that the value cannot be changed through an AIX command
interface):
frequency
..
4208000000
........
Processor Speed False
smt_enabled true
.......
Processor SMT enabled False
smt_threads 2
.......
Processor SMT threads False
state
......
enable
.
Processor state False
type
......
powerPC_POWER6
Processor type False
pmcycles -m
The
pmcycles
command (available with AIX) uses the performance monitor cycle counter
and the processor real-time clock to measure the actual processor clock speed in MHz.
The following output is from a 4-core 570 system running at 4.2 GHz with simultaneous
multithreading enabled:
Cpu 0 runs at 4208 MHz
Cpu 1 runs at 4208 MHz
Cpu 2 runs at 4208 MHz
Cpu 3 runs at 4208 MHz
Cpu 4 runs at 4208 MHz
Cpu 5 runs at 4208 MHz
Cpu 6 runs at 4208 MHz
Cpu 7 runs at 4208 MHz
2.4 Memory subsystem
When you consider a 570 initial order, the memory controller is internal to the POWER6
processor and it interfaces any of the memory buffer chips within the pluggable fully buffered
DIMMs (12 slots available per processor card, as described in 1.3.2, “Memory features” on
page 6).
2.4.1 Fully buffered DIMM
Fully buffered DIMM is a memory technology which can be used to increase reliability, speed
and density of memory subsystems. Conventionally, data lines from the memory controller
have to be connected to data lines in every DRAM module. As memory width, as well as
access speed, increases, the signal degrades at the interface of the bus and the device. This
limits the speed or the memory density. The fully buffered DIMMs take a different approach
because directs signaling interface between the memory controller and the DRAM chips,
splitting it into two independent signaling interfaces with a buffer between them. The interface
Note:
Any system made of more than one processor card must have all processor cards
running at the same speed.
Note:
The
pmcycles
command is part of the bos.pmapi fileset. Use the
lslpp -l
bos.pmapi
command to determine if it is installed on your system.
