IBM eServer OpenPower 720, Технический обзор и введение

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© Copyright IBM Corp. 2004. All rights reserved.
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Chapter 2.
Architecture and technical
overview
This chapter discusses the overall system architecture represented by Figure 2-1. The major
components of this diagram are described in the following sections. The bandwidths provided
throughout this section are theoretical maximums provided for reference. It is always
recommended to obtain real-world performance measurements using production workloads.
Figure 2-1 OpenPower 720 logic data flow
2
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SMI-II SMI-II
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shared L2 cache
distributed switch
core core
L3
cache
DCM
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memory
controller
Vertical Fabric
bus
2 (Proc Clk):1
8 Bytes each dir
Elastic Intfc
2 (Proc Clk):1
8 Bytes each dir
Elastic Intfc
Enterprise
RIO HUB
Enterprise
RIO HUB
RIO-2 expansion
card
RIO-2 bus
2 B (Diff'l) each dir
1 GB/sec
GX+ bus
3 (Proc Clk):1
4 Bytes each dir
Elastic Intfc
GX+ bus
3 (Proc Clk):1
4 Bytes each dir
Elastic Intfc
RIO-2 bus
2 B (Diff'l) each dir
1 GB/sec
PCI-X Host
bridge
RIO-2 bus
2 B (Diff'l) each dir
1 GB/sec
PCI-X to PCI-X
bridge 2
PCI-X to PCI-X
bridge 0
PCI-X slot #5 #4 #3 #2 #1
133 MHz
optional media backplane
slim-line media device
slim-line media device
Dual SCSI
Ultra320
IDE
controller
SP
operator panel
133 MHz
66 MHz
33 MHz
100 MHz
RAID
enablement
card
Two
Ethernet
ports
Dual 1 GB
Ethernet
USB
Two USB
ports
Two HMC
Eth ports
Two SPCN
ports
4-pack disk drive backplane
shared L2 cache
memory
controller
distributed switch
core core
L3
cache
DCM
POWER5 POWER5
Two SP communication
ports
*DDR1 memory *DDR1 memory
interface card
CUoD key card
133 MHz
to operator panel
from optional
media backplane
4-pack disk drive backplane
133 MHz
133 MHz
133 MHz
GX+ slot
Tape
bus0 1