IBM DTTA-350320, Технические характеристики

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DD00-DD15 16-bit bi-directional data bus between the host and the H D D . The lower 8 lines, DD00-07,
are used for Register and ECC access. All 16 lines, DD00-15, are used for data transfer.
These are 3-State lines with 24 mA current sink capability.
DA00-DA02 Address used to select the individual register in the H D D .
-CS0 Chip select signal generated from the Host address bus. When active, one of the Command
Block Registers (Data, Error{Features when written}, Sector Count, Sector Number, Cyl-
inder Low, Cylinder High, Drive/Head and Status{Command when written} register) can be
selected.
(SeeFigure 29 on page 37 .)
-CS1 Chip select signal generated from the Host address bus. When active, one of the Control
Block Registers (Alternate Status{Device Control when written} and Drive Address register)
can be selected.
(SeeFigure 29 on page 37 .)
-RESET This line is used to reset the H D D . It shall be kept Low logic state during power up and
kept High thereafter.
-DIOW Its rising edge holds data from the host data bus to a register or data register of the H D D .
-DIOR When low, this signal enables data from a register or data register of the drive onto data bus.
The data on the bus shall be latched on the rising edge of -DIOR.
INTRQ Interrupt is enabled only when the drive is selected, and the host activates the -IEN bit in
the Device Control Reg. Otherwise, this signal is in high impedance state regardless of the
state of the I R Q bit. The interrupt is set when the I R Q bit is set by the drive CPU. I R Q is
reset to zero by a host read of the status register or a write to the Command Reg. This
signal is a 3-State line with 24 mA sink capability.
-HIOCS16 Indication to the host that a 16-bit wide data register has been addressed and that the drive
is prepared to send or receive a 16-bit wide data word. This signal is an Open-Drain output
with 24 mA sink capability and an external resistor is needed to pull this line to 5 volts.
-DASP This is a time-multiplexed signal which indicates that a drive is active, or that device 1 is
present.
This signal is driven by Open-Drain driver and internally pulled-up to 5 volts
through a 10k
Ω
resistor.
During Power-On initialization or after -RESET is negated, -DASP shall be asserted by
Device 1 within 400 msec to indicate that device 1 is present.
Device 0 shall allow up to
450msec for device 1 to assert -DASP. If device 1 is not present, device 0 may assert -DASP
to drive a L E D indicator.
-DASP shall be negated following acceptance of the first valid command by device 1.
Anytime after negation of -DASP, either drive may assert -DASP to indicate that a drive is
active.
-PDIAG This signal shall be asserted by device 1 to indicate to device 0 that it has completed diag-
nostics. This line is pulled-up to 5 volts in the H D D through a 10k
Ω
resistor.
Following a Power On Reset, software reset or -RESET, drive 1 shall negate -PDIAG
within 1 msec (to indicate to device 0 that it is busy).
Drive 1 shall then assert -PDIAG
within 30 seconds to indicate that it is no longer busy, and is able to provide status.
Following the receipt of a valid Execute Drive Diagnostics command, device 1 shall negate
-PDIAG within 1 msec to indicate to device 0 that it is busy and has not yet passed its drive
diagnostics. If device 1 is present then device 0 shall wait up to 6 seconds from the receipt
of a valid Execute Drive Diagnostics command for drive 1 to assert -PDIAG.
Device 1
should clear BSY before asserting -PDIAG, as -PDIAG is used to indicate that device 1 has
passed its diagnostics and is ready to post status.
If -DASP was not asserted by device 1 during reset initialization, device 0 shall post its own
status immediately after it completes diagnostics, and clear the device 1 Status register to
Specification
21