IBM CPC700, Руководство пользователя

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4-8 Memory Controller
4.5.4 SDRAM Configuration Registers
The SDRAM configuration registers are listed in Table 25.
Detailed descriptions of these registers can be found in Section 4.9, “Memory Controller Register Descrip-
tion”.
4.5.5 Physical Address to Memory Mapping
The tables below show the mapping of the processor’s physical address to the memory address for all local
processor and PCI to memory accesses when using SDRAM. This mapping of the processor’s physical ad-
dress to the CPC700’s Bank Address (BA[1:0]) and Memory Address (MA[12:0]) pins is done by the
CPC700 on a per bank basis based on the mode settings in the DRAM Addressing Mode (DAM) registers.
4.5.5.1 32-Bit Memory Mapping
The following tables specify the organization of the SDRAM as follows: ROW x COLUMN (INTERNAL
BANKS).
AP = 1 if Auto-Precharge is enabled, AP = 0 if Auto-Precharge is disabled. This bit field corresponds
directly to SD_APGE from the SDTR1 configuration register.
All shaded entries are "don’t care" for the particular addressing mode, but will be driven with the value indi-
cated to minimize internal muxing of individual address bits for the addressing modes supported.
SDRAM address pins names (BA[1:0] and MA[12:0]) are shown using little endian nomenclature.
Table 25. SDRAM Configuration Registers
Register
Symbol
Register Name
MCOPT1 Memory Controller Options 1
MEMTYPE Memory Type
MBEN Memory Bank Enable
MBSA0 -
MBSA4 Memory Bank Starting Addresses
MBEA0 -
MBEA4 Memory Bank Ending Addresses
SDTR1 SDRAM Memory Timing Register 1
DAM DRAM Addressing Mode
RWD Bank Active Watchdog Timer
RTR Refresh Timer Register
ECCCF ECC Configuration Register (bit 4, SD_WDTH, sets SDRAM bus width to 32 or
64-bit)