IBM 9123710 - eServer OpenPower 710, Руководство по введению, Страница: 26 / 70

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IBM eServer OpenPower 710 Technical Overview and Introduction
2.1 The POWER5 chip
The POWER5 chip features single and simultaneous multi-threaded execution, providing
higher performance in the single-threaded mode than its POWER4™ predecessor at
equivalent frequencies. The POWER5 processor maintains both binary and architectural
compatibility with existing POWER4 processor-based systems and is designed to ensure that
binaries continue executing properly and application optimizations carry forward to newer
systems. Table 2-1 shows highlights and changes between the POWER4 and the POWER5
processor.
Table 2-1 POWER4 to POWER5 comparison
POWER5 design provides additional enhancements such as virtualization, reliability,
availability, and serviceability (RAS) features at both chip and system levels.
Key enhancements introduced into the POWER5 processor and system design include:
򐂰 Simultaneous multi-threading
򐂰 Dynamic resource balancing to efficiently allocate system resources to each thread
򐂰 Software-controlled thread prioritization
򐂰 Dynamic power management to reduce power consumption without affecting performance
򐂰 Micro-Partitioning technology
򐂰 Virtual storage, virtual Ethernet
򐂰 Enhanced scalability, parallelism
򐂰 Enhanced memory subsystem
Figure 2-2 on page 17 shows the high-level structures of POWER5 processor-based
systems. POWER5 processor supports a 1.9 MB on-chip L2 cache, implemented as three
identical slices with separate controllers for each. Either processor core can independently
access each L2 controller. The L3 cache, with a capacity of 36 MB, operates as a backdoor
with separate buses for reads and writes that operate at half processor speed.
POWER4 design POWER5 design
L1 data cache 2-way set associative FIFO
a
a. FIFO stands for First In First Out
4-way set associative LRU
b
b. LRU stands for Least Recently Used
L2 cache 8-way set associative 1.44 MB 10-way set associative 1.9 MB
L3 cache 32 MB
118 clock cycles 36 MB
~80 clock cycles
Memory bandwidth 4 GB/second /chip ~16 GB/second /chip
Simultaneous
multi-threading No Yes
Processor addressing 1 processor 1/10th of processor
Dynamic power
management No Yes
Size 412 mm 389 mm