IBM 6275 - PC 300 GL, Техническое руководство

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Chapter 2. System-Board Features
Figure 1. Memory Configurations
Total Memory (MB) Mem 0 Mem 1 Mem2
16 16 0 0
32 16 16 0
32 32 0 0
48 16 16 16
48 32 16 0
64 32 16 16
64 32 32 0
64 64 0 0
96 32 32 32
96 64 32 0
128 64 32 32
128 64 64 0
128 128 0 0
160 32 64 64
192 64 64 64
224 32 64 128
256 128 64 64
256 128 128 0
288 32 128 128
384 128 128 128
PCI Bus
The fully synchronous 33 MHz PCI bus originates in the chip set. Features of the PCI bus are:
Integrated arbiter with multi-transaction PCI arbitration acceleration hooks for high performance
graphics
Built-in PCI bus arbiter with support for up to five masters
Microprocessor-to-PCI memory write posting with 5-Dword-deep buffers
Converts back-to-back sequential microprocessor-to-PCI memory write to PCI burst write
PCI-to-DRAM posting 18 Dwords
PCI-to-DRAM up to 100+ MB/sec bandwidth
Multitransaction timer to support multiple short PCI transactions within one PCI ARB cycle
PCI 2.1 compliant
Delayed transaction
PCI parity checking and generation support
IDE Bus Master Interface
The system board incorporates a PCI-to-IDE interface that complies with the AT Attachment Interface with
Extensions.
The Intel PIIX4E functions as a bus master for the IDE interface. The chip set is PCI 2.1 compliant; it
connects directly to the PCI bus and is designed to allow concurrent operations on the PCI bus and IDE
bus. The chip set is capable of supporting PIO mode 0–4 devices and IDE DMA mode 0–2 devices, ultra
DMA 33 transfers up to 33 Mbytes/sec.
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Technical Information Manual