
114
8. SCON-C
63
5.5 Assignment of DeviceNet Addresses
Output po
rt No.
(bit add
re
ss
)
PLC input buf
fer memo
ry
(bit position)
Nod
e add
re
ss
PLC output b
uffer memo
ry
(bit position)
Input port No.
(bit add
re
ss
)
•
The abo
ve fig
ure a
ssume
s
that the node
address of
the
controlle
r’s
De
viceNet
bo
ard
is
set
to
“0.”
•
I/O ports are assign
ed in u
nits of 16 poi
nts to the me
mory are
a
co
rre
sp
ondi
ng to one Devi
ce
Net nod
e add
ress.
•
I/P ports are
assign
ed seq
uentiall
y from
the youn
ge
st numbe
r, to the bits in the
buffer memo
ry sta
rting fro
m
the
lower b
it.
8.5
Содержание DeviceNet ASEL Series
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