HYT TC-700 Ex PLUS, Руководство по обслуживанию

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TC-700 EX PLUS Service Manual
16
Fig.2 PLL Block Diagram
1) PLL Circuit
Step frequency of PLL can be 2.5 KHz, 5.0 KHz or 6.25 KHz. A 16.8MHz reference oscillator signal is
divided at IC301 by a counter to generate a 2.5 KHz, 5.0 KHz or 6.25 KHz reference frequency. Output
signal from VCO is buffer amplified by Q301 and divided at IC301 by a frequency divider. The divided
signal is compared with 2.5 KHz, 5.0 KHz or 6.25 KHz reference signal in the phase comparator of IC301.
The output signal from phase comparator is filtered through a low pass filter to generate a level D.C., and
the level D.C. controls oscillator frequency by controlling VCO.
2) VCO
The operating frequency is generated by Q302 in transmit mode and by Q307 in receive mode.
Operating frequency generate a control voltage by phase comparator to control varactor so that the
oscillator frequency is consistent with the MCU preset frequency (D301 、 D302 、 D303 and D304 in
transmit mode, and D307
、
D308
、
D309 and D310 in receive mode). T/R pin is set high level in receive
mode, and low level in transmit mode. The output from Q302 and Q307 is amplified by Q304 and sent to
buffer amplifier.
3) Unlock Detector
An unlock condition appears if low level occurs at MUXOUT pin of IC301. Transmission is inhibited if this
condition is detected by microprocessor.
3. Receiver
The receiver utilizes double conversion superheterodyne (UHF)/(VHF).
VCO
MCU
PLL
SW
D201
BUFF
Q301
SW
D101
BUFF
Q111
CLK,DAT,STB
T/R
CV
To Drive Amp
To Mixer
VCXO
X301
CTC
UL
1st Local OSC