TC- 446 Service Manual
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10
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6)
Receive signaling
CTCSS/CDCSS
Audio frequencies over 300Hz of the output signal from IC1 is cut off by a low-pass filter. The
resulting signal enters the microprocessor IC11. IC11 determines whether the CTCSS/CDCSS
matches the preset value and controls the MUTE and AFCO and the speaker sound output
according to the squelch results.
3.
PLL Frequency Synthesizer
PLL circuit generates the first local oscillator signal for reception and the RF signal for
transmission.
1) PLL Circuit
The step frequency of PLL circuit is 2.5KHz or 6.25 KHz. A12.8MHz reference
oscillator signal is divided at IC2 by a fixed counter to produce a 2.5 KHz or 6.25 KHz
reference frequency. Output signal from voltage control oscillator (VCO) passes
through buffer amplifier Q14 and is divided at IC2 by the dual-module programmable
counter. The divided signal is compared in the phase comparator IC2 with the 2.5 KHz
or 6.25 KHz reference signal. The output signal from phase compara tor is filtered
through a low-pass filter and passed to the VCO to control the oscillator frequency.
(See figure 4)
Figure 4 PLL circuit
2) VCO
The operating frequency is generated by Q16 in transmit mode and by Q8 in receive
mode. The operation frequency generates a voltage through the phase comparator to
control the varactor diodes, so as to keep the oscillator frequency consistent with the
preset frequency in CPU (D2 and D3 in transmit mode and D7 and D8 in receive mode).
T/R pin is set high in receive mode causing Q6 to turn off Q16 and turn Q7 on. The T/R pin is set
low in transmit mode. The output from Q8 and Q16 is amplified by Q14 and sent to the buffer
amplifier.
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