TC-268/368 Service Manual
11
FM IF IC200
IF AMP
DET
DET
HPF
AMP
IC 300
AF AMP
LPF
HPF
Q302
SW
IC302
AF/PF AMP
Q307
SW
SP
Q304.Q305.Q306
SW
Q303
W/N SW
IC301
LPF
5
62
67
6
BUSY
MUTE
AF
CO
TI
IC403
MPU
Fig. 3. AF Amplifier and squelch
6) Receiving signaling
CTCSS/CDCSS
300 Hz and higher audio frequencies of the output signal from IF IC are cut by a low-pass filter
(IC301). The resulting signal enters the microprocessor (IC403). IC403 determines whether the CTCSS
or CDCSS matches the preset value, and controls the MUTE and AFCO and the speaker output sounds
according to the squelch results.
3. PLL frequency synthesizer
The PLL circuit generates the first local oscillator signal for reception and the RF signal for
transmission.
1) PLL
The frequency step of the PLL circuit is 5 or 6.25kHz. A 12.8MHz reference oscillator signal is divided
at IC1 by a fixed counter to produce the 5 or 6.25kHz reference frequency. The voltage controlled
oscillator (VCO) output signal is buffer amplified by Q6, then divided in IC1 by a dual-module
programmable counter. The divided signal is compared in phase with the 5 or 6.25kHz reference signal
in the phase comparator in IC1. The output signal from the phase comparator is filtered through a
low-pass filter and passed to the VCO to control the oscillator frequency. (See Fig. 4 of Next Page)
B
C
D
D
C
B
PLL DATA
PLL IC IC1
I/N
5KHz/6.25KHz
PHASE
COMPARATOR
REF OSC
12.8MHz
I/M
5KHz/6.25KHz
CHARGE
LPF
D2.4
Q4
TX VCO
D1.3
Q3
RX VCO
Q6
BUFF AMP
Q5.7
T/R SW
Q2
RF AMP
PUMP
Fig. 4. PLL circuit
Содержание TC-268
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