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Hynix HMT112S6TFR8C, Руководство пользователя

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APCPCWM_4828539:WP_0000005WP_0000005

A

P

C

P

C

W

M

_4828539:

W

P

_0000005W

P

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5

Rev. 1.2 / Jul. 2010

48 

256Mx64 - HMT125S6TFR8C

Front

Back

30.

0mm 

67.60mm

20.

0mm 

6.00

2.0

21.00

39.00

2.15

3.00

pin 1

pin 203

Detail- 

A

SPD

3.80mm max

Detail-B

4.00 0.10

1.65 0.10

1.00         mm

0.08

1.80 0.10

2

X

Side

Note: 
1.          tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

2.5

5

1.00

Detail of Contacts A

0.3

0.3~1.0

0.

1

5

0.05

0.45

 

0.03

4.00

 

0.

1

0

0.60

B48614/178.104.2.80/2010-07-08 11:46

Содержание HMT112S6TFR8C

Страница 1: ...2 Jul 2010 1 204pin DDR3 SDRAM SODIMM Hynix Semiconductor reserves the right to change products or specifications without notice DDR3 SDRAM Unbuffered SODIMMs Based on 1Gb T die HMT112S6TFR8C HMT125S6...

Страница 2: ...ision History Revision No History Draft Date Remark 0 1 Initial Release Sep 2009 Preliminary 1 0 JEDEC Update Nov 2009 Web posting 1 1 Add supported CL5 Jun 2010 Web posting 1 2 DIMM Outline Corrected...

Страница 3: ...s product is in compliance with the RoHS directive Ordering Information Part Number Density Organization Component Composition of ranks HMT112S6TFR8C G7 H9 1GB 128Mx64 128Mx8 H5TQ1G83TFR 8 1 HMT125S6T...

Страница 4: ...066 G7 1 875 7 13 125 13 125 37 5 50 625 7 7 7 DDR3 1333 H9 1 5 9 13 5 13 5 36 49 5 9 9 9 Grade Frequency MHz Remark CL5 CL6 CL7 CL8 CL9 CL10 G7 667 800 1066 1066 H9 667 800 1066 1066 1333 1333 1GB 1R...

Страница 5: ...event pin 1 WE Write Enable 1 TEST Logic Analyzer specific test pin No connect on SODIMM 1 S 1 0 Chip Selects 2 RESET Reset Pin 1 A 9 0 A11 A 15 13 Address Inputs 14 VDD Core and I O Power 18 A10 AP A...

Страница 6: ...es the column address when sampled at the cross point of the rising edge of CK and falling edge of CK In addition to the column address AP is used to invoke autoprecharge operation at the end of the b...

Страница 7: ...Active Low This signal indicates that a thermal event has been detected in the thermal sensing device The system should guarantee the electrical level requirement is met for the EVENT pin on TS SPD pa...

Страница 8: ...VSS 77 NC 78 A152 129 DQ32 130 DQ36 181 DQ56 182 DQ61 27 DQS1 28 DM1 79 BA2 80 A142 131 DQ33 132 DQ37 183 DQ57 184 VSS 29 DQS1 30 RESET 81 VDD 82 VDD 133 VSS 134 VSS 185 VSS 186 DQS7 31 VSS 32 VSS 83...

Страница 9: ...DQS3 DM3 Q 48 55 DQS DQS DM DQ 0 7 D3 240ohm ZQ 1 RAS CAS CS WE CK CK CKE ODT A O N BA O N LDQS LDQS LDM DQ 0 7 D7 240ohm ZQ 1 RAS CAS CS WE CK CK CKE ODT A O N BA O N DQS1 DQS1 DM1 DQ 8 15 DQS3 DQS3...

Страница 10: ...WE CK CK CKE ODT A O N BA O N DQS4 DQS4 DM4 DQ 32 39 DQS6 DQS6 DM6 DQ 48 55 DQS7 DQS7 DM7 DQ 56 43 DQS5 DQS5 DM5 DQ 40 47 Vtt Vtt VDD VDD Cterm Cterm D12 D4 DQS DQS DM DQ 0 7 240ohm ZQ 1 RAS CAS CS WE...

Страница 11: ...l operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature Full specifications are guaranteed in this range but t...

Страница 12: ...C by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Recommended DC Operating Conditions Symbol Parameter Rating Units Notes Min Typ Max VDD Supply Voltage 1 425 1 500 1...

Страница 13: ...to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Single Ended AC and DC Input Levels for DQ and DM Symbol Parameter DDR3 800 1066 DDR3 1333 U...

Страница 14: ...d time measurements VIH AC VIH DC VIL AC and VIL DC are depen dent on VRef VRef shall be understood as VRef DC as defined in figure above This clarifies that dc variations of VRef affect the absolute...

Страница 15: ...Differential Signals Differential signal definition Definition of differential ac swing and time above ac level tDVAC time Differential Input Voltage i e DQS DQS CK CK VIL DIFF AC MAX VIL DIFF MAX 0...

Страница 16: ...in for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 25 Differential AC and DC Input Levels Symbol Parameter DD...

Страница 17: ...D and DQ s might be different per speed bin etc E g if VIH CA AC150 VIL CA AC150 is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK Single ended require...

Страница 18: ...al Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and...

Страница 19: ...for Single Ended Input Signals See 7 5 Address Command Setup Hold and Derating on page 137 in DDR3 Device Operation for sin gle ended slew rate definitions for address and command signals See 7 6 Data...

Страница 20: ...e Definition for DQS DQS and CK CK Differential Input Slew Rate Definition Description Measured Defined by Min Max Differential input slew rate for rising edge CK CK and DQS DQS VILdiffmax VIHdiffmin...

Страница 21: ...mpedance of 40 and an effective test load of 25 to VTT VDDQ 2 at each of the differential outputs Single ended AC and DC Output Levels Symbol Parameter DDR3 800 1066 1333 Unit Notes VOH DC DC output h...

Страница 22: ...ery Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Single ended Output slew Rate Definition Description Measured Defined by From To Single ended...

Страница 23: ...OLdiff AC DeltaTRdiff Differential output slew rate for falling edge VOHdiff AC VOLdiff AC VOHdiff AC VOLdiff AC DeltaTFdiff Notes 1 Output slew rate is verified by design and characterization and may...

Страница 24: ...esentation of any particular system environment or a depiction of the actual load presented by a production tester System designers should use IBIS or other simulation tools to correlate the timing re...

Страница 25: ...allowed for overshoot area See figure below 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See figure below 0 4 0 4 0 4 V Maximum overshoot area above VDD See figure below 0 67 0 5...

Страница 26: ...vershoot area See figure below 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See figure below 0 4 0 4 0 4 V Maximum overshoot area above VDD See figure below 0 25 0 19 0 15 V ns Max...

Страница 27: ...parameters by device density Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units REF command ACT or REF command time tRFC 90 110 160 300 350 ns Average periodic refresh interval tREFI 0 C TCASE 85...

Страница 28: ...3 800E Unit Notes CL nRCD nRP 6 6 6 Parameter Symbol min max Internal read command to first data tAA 15 20 ns ACT to internal read or write delay time tRCD 15 ns PRE command period tRP 15 ns ACT to AC...

Страница 29: ...ns PRE command period tRP 13 125 ns ACT to ACT or REF command period tRC 50 625 ns ACT to PRE command period tRAS 37 5 9 tREFI ns CL 5 CWL 5 tCK AVG 3 0 3 3 ns 1 2 3 4 6 10 CWL 6 tCK AVG Reserved ns...

Страница 30: ...REFI ns CL 5 CWL 5 tCK AVG 3 0 3 3 ns 1 2 3 4 7 10 CWL 6 7 tCK AVG Reserved ns 4 CL 6 CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 7 CWL 6 tCK AVG Reserved ns 1 2 3 4 7 CWL 7 tCK AVG Reserved ns 4 CL 7 CWL 5 tCK AV...

Страница 31: ...this set ting is supported 6 Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Cha...

Страница 32: ...aximum rating conditions for extended periods may affect reliablility 2 Up to 9850 ft 3 The designer must meet the case temperature specifications for individual module components Symbol Parameter Rat...

Страница 33: ...e value are guaranteed by design and tested on a sample basis only Pin Symbol Min Max Unit CK0 CK0 CCK TBD TBD pF CKE ODT CS CCTRL TBD TBD pF Address RAS CAS WE CI TBD TBD pF DQ DM DQS DQS CIO TBD TBD...

Страница 34: ...IO power to actual IO power as outlined in Figure 2 In DRAM module application IDDQ cannot be measured separately since VDD and VDDQ are using one merged power layer in Module PCB For IDD and IDDQ mea...

Страница 35: ...lation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement VDD DDR3 SDRAM VDDQ RESET CK CK DQS DQS CS RAS CAS WE A BA ODT ZQ VSS VSSQ DQ DM TDQS TDQS CKE RTT 25 Oh...

Страница 36: ...nRAS CL see Table 1 BL 8a AL 0 CS High between ACT and PRE Command Address Bank Address Inputs partially toggling according to Table 3 Data IO MID LEVEL DM stable at 0 Bank Activity Cycling with one b...

Страница 37: ...2P1 Precharge Power Down Current Fast Exit CKE Low External clock On tCK CL see Table 1 BL 8a AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID_LEVEL DM stable at 0 Bank...

Страница 38: ...ils see Table 8 IDD5B Burst Refresh Current CKE High External clock On tCK CL nRFC see Table 1 BL 8a AL 0 CS High between REF Command Address Bank Address Inputs partially toggling according to Table...

Страница 39: ...CKE Low External clock Off CK and CK LOW CL see Table 1 BL 8a AL 0 CS Command Address Bank Address Inputs Data IO MID_LEVEL DM stable at 0 Bank Activity Auto Self Refresh operation Output Buffer and R...

Страница 40: ...repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 00 0 0 F 0 1 nRC 1 2 D D 1 0 0 0 0 0 00 0 0 F 0 1 nRC 3 4 D D 1 1 1 1 0 0 00 0 0 F 0 repeat pattern 1 4 until 1 nRC nRAS 1...

Страница 41: ...cate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 00 0 0 F 0 1 nRC 1 2 D D 1 0 0 0 0 0 00 0 0 F 0 1 nRC 3 4 D D 1 1 1 1 0 0...

Страница 42: ...stead 3 12 15 repeat Sub Loop 0 use BA 2 0 3 instead 4 16 19 repeat Sub Loop 0 use BA 2 0 4 instead 5 20 23 repeat Sub Loop 0 use BA 2 0 5 instead 6 24 17 repeat Sub Loop 0 use BA 2 0 6 instead 7 28 3...

Страница 43: ...0 1 0 1 0 0 00 0 0 F 0 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 6 7 D D 1 1 1 1 0 0 00 0 0 F 0 1 8 15 repeat Sub Loop 0 but BA 2 0 1 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA...

Страница 44: ...Datab toggling Static High 0 0 REF 0 0 0 1 0 0 0 0 0 0 0 1 1 2 D D 1 0 0 0 0 0 00 0 0 0 0 3 4 D D 1 1 1 1 0 0 00 0 0 F 0 5 8 repeat cycles 1 4 but BA 2 0 1 9 12 repeat cycles 1 4 but BA 2 0 2 13 16 re...

Страница 45: ...1 if necessary 5 nFAW repeat Sub Loop 0 but BA 2 0 4 6 nFAW nRRD repeat Sub Loop 1 but BA 2 0 5 7 nFAW 2 nRRD repeat Sub Loop 0 but BA 2 0 6 8 nFAW 3 nRRD repeat Sub Loop 1 but BA 2 0 7 9 nFAW 4 nRRD...

Страница 46: ...D2N 240 280 mA IDD2NT 280 320 mA IDD2P0 80 80 mA IDD2P1 200 280 mA IDD2Q 240 280 mA IDD3N 280 320 mA IDD3P 160 200 mA IDD4R 720 840 mA IDD4W 720 840 mA IDD5B 1080 1120 mA IDD6 80 80 mA IDD6ET 96 96 mA...

Страница 47: ...0mm 20 0mm 6 00 2 0 21 00 39 00 2 15 3 00 pin 1 pin 203 Detail A 3 80mm max 4 00 0 10 1 65 0 10 1 00 mm 0 08 1 80 0 10 2X Note 1 tolerance on all dimensions unless otherwise stated 0 13 Units millimet...

Страница 48: ...0 21 00 39 00 2 15 3 00 pin 1 pin 203 Detail A SPD 3 80mm max Detail B 4 00 0 10 1 65 0 10 1 00 mm 0 08 1 80 0 10 2X Side Note 1 tolerance on all dimensions unless otherwise stated 0 13 Units millimet...

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