APCPCWM_4828539:WP_0000005WP_0000005
A
P
C
P
C
W
M
_4828539:
W
P
_0000005W
P
_000000
5
Rev. 1.2 / Jul. 2010
19
Notes:
1. Extended range for V
IX
is only allowed for clock and if single-ended clock input signals CK and CK are
monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential
slew rate of CK - CK is larger than 3 V/ns.
2. Refer to the table “Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU” on page 18
for VSEL and VSEH standard values.
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Derating” on page 137 in “DDR3 Device Operation” for sin-
gle-ended slew rate definitions for address and command signals.
See 7.6 “Data Setup, Hold and Slew Rate Derating” on page 144 in “DDR3 Device Operation” for single-
ended slew rate definition for data signals.
Cross point voltage for differential input signals (CK, DQS)
Symbol
Parameter
DDR3-800, 1066, 1333
Unit Notes
Min
Max
V
IX
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK
-150
150
mV
-175
175
mV
1
V
IX
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS
-150
150
mV
B48614/178.104.2.80/2010-07-08 11:46
