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HMS8132E/HMS81032TL

Nov. 2001 Ver 2.00

47

14.1 Interrupt priority and sources

Each interrupt vector is independent and has its own pri-
ority. Software interrupt (BRK) is also available. Interrupt

source classification is shown in Table 14-1.

14.2 Interrupt control register

I flag of PSW is a interrupt mask enable flag. When I flag
= “0”, all interrupts become disable. When I flag = “1”, in-
terrupts can be selectively enabled and disabled by con-
tents of corresponding Interrupt Enable Register. When
interrupt is occurred, interrupt request flag is set, and Inter-
rupt request is detected at the edge of interrupt signal. The
accepted interrupt request flag is automatically cleared

during interrupt cycle process. The interrupt request flag
maintains “1” until the interrupt is accepted or is cleared in
program. In reset state, interrupt request flag register
(IRQH, IRQL) is cleared to “0”. It is possible to read the
state of interrupt register and to manipulate the contents of
register and to generate interrupt. (Refer to software inter-
rupt)

Mask

Priority

Reset/Interrupt

Symbol

INT Vector H

INT Vector L

Hardware Interrupt

Non-maskable

-

Hardware Reset

RESET

FFFF

FFFE

maskable

1

Key Scan

KSCNR

FFFB

FFFA

2

External Interrupt1

INT1R

FFF9

FFF8

3

External Interrupt2

INT2R

FFF7

FFF6

4

Timer0

T0R

FFF3

FFF2

5

Timer1

T1R

FFF1

FFF0

6

Timer2

T2R

FFEF

FFEE

7

Watch Dog Timer

WDTR

FFE9

FFE8

8

Basic Interval Timer

BITR

FFE7

FFE6

Software Interrupt

-

-

BRK Instruction

BRK

FFDF

FFDE

Table 14-1 Interrupt Source

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Содержание HMS81004E

Страница 1: ...HYNIX SEMICONDUCTOR 8 BIT SINGLE CHIP MICROCONTROLLERS HMS81004 08 16 24 32E HMS81020 32TL User s Manual Ver 2 00...

Страница 2: ...ynix Semiconductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this manual are correct and reliable however Hyni...

Страница 3: ...TERRUPTS 46 Interrupt priority and sources 47 Interrupt control register 47 Interrupt accept mode 48 Interrupt Sequence 49 BRK Interrupt 51 Multi Interrupt 51 External Interrupt 51 Key Scan Input Proc...

Страница 4: ...HMS81032E HMS81032TL NOV 2001 Ver 2 00...

Страница 5: ...saving modes to reduce power consumption 1 2 Features Instruction Cycle Time 1us at 4MHz Programmable I O pins Operating Voltage 2 0 3 6 V 4MHz MASK 2 0 4 0 V 4MHZ OTP Timer Timer Counter 16Bit 1ch 8B...

Страница 6: ...ler an in circuit emulator CHOICE Dr TM and OTP programmers Macro assembler operates under the MS Windows 95 98TM NT4 W2000 Please contact sales part of HYNIX Software MS Window base assembler Linker...

Страница 7: ...M 448byte ROM 32kbyte Prescaler B I T Watchdog Timer Timer Interrupt Key Scan INT Generation Block Clock Gen System Control R0 PORT R1 PORT R2 PORT REMOUT R17 T0 R16 T1 R15 T2 R14 EC R12 INT2 R11 INT1...

Страница 8: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R13 R12 R11 R10 VDD XOUT XIN R00 R01 R02 R03 R20 R14 R15 R16 R17 REMOUT RESET TEST R07 R06 R05 R04 VSS 24PIN 1 2 3 4 5 6 7 8...

Страница 9: ...043 0 021 0 065 0 100 BSC 0 300 BSC 0 270 0 012 0 15 MAX 0 180 MIN 0 015 0 140 0 512 0 020 0 050 BSC 0 0 1 3 0 8 0 042 20 PDIP 20 SOP UNIT INCH MAX MIN 1 015 0 015 0 050 0 120 0 245 0 008 0 299 0 291...

Страница 10: ...0 065 0 100 BSC 0 300 BSC 0 300 0 014 0 15 MAX 0 180 MIN 0 015 0 140 0 614 0 020 0 050 BSC 0 0 1 3 0 8 0 042 24 SKDIP 24 SOP UNIT INCH MAX MIN 1 160 0 015 0 045 0 120 0 250 0 008 0 299 0 291 0 419 0 3...

Страница 11: ...0 055 0 100 BSC 0 300 BSC 0 300 0 014 0 15 MAX 0 180 MIN 0 020 0 140 0 713 0 020 0 050 BSC 0 0 1 3 0 8 0 042 28 SKDIP 28 SOP UNIT INCH MAX MIN 1 355 0 015 0 045 0 120 0 275 0 008 0 299 0 291 0 419 0 3...

Страница 12: ...en to the Port Direction Register can be used as outputs or inputs R10 R17 R1 is an 8 bit CMOS bidirectional I O port R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or in...

Страница 13: ...rogrammable as key scan input or open drain output Pull up resisters are automatically disabled at output mode Direct driving of LED N Tr INPUT State of before Stop R11 INT1 I O R12 INT2 I O R13 I O R...

Страница 14: ...unction Sele Key Scan Pull up Reg Rd VDD VSS Pull up Tr Input Open Drain Reg Data Bus Tr Transistor Reg Register LVD Circuit OTP connected MASK option default connected VDD KS_EN Standby Release Level...

Страница 15: ...ASK option default connected VDD KS_EN Standby Release Level Control Register ction Reg Dir Reg MUX to R15 T2 to R16 T1 to R17 T0 MUX MUX Pin Data Reg Dir Reg Pull up Reg Rd VDD VSS Pull up Tr Open Dr...

Страница 16: ...2 0 3 6V GND 0V Parameter Symbol Condition Specifications Unit Min Max Supply Voltage VDD fXIN 4MHz 2 0 3 6 V Operating Frequency fXIN VDD 2 0 3 6V 1 0 4 0 MHz Operating Temperature TOPR 0 70 C Parame...

Страница 17: ...ting current fxin 4Mhz VDD 2 0V 2 4 6 mA IDD2 Operating current fxin 4Mhz VDD 3 6V 4 10 mA ISLP1 Sleep mode current fxin 4Mhz VDD 2 0V 1 2 mA ISLP2 Sleep mode current fxin 4Mhz VDD 3 6V 2 3 mA ISTP1 S...

Страница 18: ...0 ns System clock cycle time tSYS 500 1000 2000 ns External clock pulse width High tCPH XIN 40 ns External clock pulse width Low tCPL XIN 40 ns External clock rising time tRCP XIN 40 ns External clock...

Страница 19: ...HMS8132E HMS81032TL Nov 2001 Ver 2 00 15 Figure 7 3 Timing Diagram tRCP tFCP XIN INT1 INT2 0 5V VDD 0 5V 0 2VDD 0 8VDD 0 2VDD RESET 0 2VDD 0 8VDD EC tIL tIH tRSTL tECL tECH tCP tCPH tCPL tREC tFEC...

Страница 20: ...y can be used as simple accumulators X Register In the case of division instruction execute as register Y Register In the case of 16 bit operation instruction execute as the upper 8 bit of YA 16 bit a...

Страница 21: ...er an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction SP 01H Stack Address 100H 1FFH 15 0 8 7 Hardware fixed Caution The Stack Pointer must be initialized by so...

Страница 22: ...g G This flag assigns RAM page for direct addressing mode In the direct addressing mode addressing area is from zero page 00H to 0FFH when this flag is 0 If it is set to 1 addressing area is 1 Page It...

Страница 23: ...interrupt causes the CPU to jump to specific location where it commences the execution of the service routine The External interrupt 0 for example is assigned to loca tion 0FFFAH The interrupt servic...

Страница 24: ...ea 192 Bytes means that the BRK software interrupt is using same address with TCALL0 NOTE TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3...

Страница 25: ...T_USED DW INT2 Int 2 DW INT1 Int 1 DW KEY_INT Key Scan DW NOT_USED DW RESET Reset ORG 08000H HMS81032E Program start address MAIN PROGRAM RESET NOP CLRG DI Disable All Interrupts LDX 0 RAM_CLR LDA 0 R...

Страница 26: ...in each peripheral section Note Write only registers can not be accessed by bit ma nipulation instruction Do not use read modify write instruc tion Use byte manipulation instruction Example To write...

Страница 27: ...IRQL R W 00 b 00CEh INT ENABLE REG HIGH IENH R W 000 000 b 00CFh INT REQUEST FLAG REG HIGH IRQH R W 000 000 b 00D0h TIMER0 16bit MODE REG TM0 R W 00000000b 00D1h TIMER1 8bit MODE REG TM1 R W 00000000...

Страница 28: ...RELEASE LEVEL CONT REG 0 SRLC0 W 00000000b 00F7h STANDBY RELEASE LEVEL CONT REG 1 SRLC1 W 00000000b 00F8h PORT R0 PULL UP REG CONT REG R0PC W 00000000b 00F9h PORT R1 PULL UP REG CONT REG R1PC W 000000...

Страница 29: ...t address which is composed of 8 bit RAM paging register RPR and 8 bit immediate data Example G 1 RPR 0CH E45535 LDM 35H 55H 3 Direct Page Addressing dp In this mode a address is specified within dire...

Страница 30: ...AM X X indexed direct page auto increment X In this mode a address is specified within direct page by the X register and the content of X is increased by 1 LDA STA Example G 0 X 35H DB LDA X X indexed...

Страница 31: ...page indirect dp Assigns data address to use for accomplishing command which sets memory data or pair memory by Operand Also index can be used with Index register X Y JMP CALL Example G 0 3F35 JMP 35...

Страница 32: ...rect page plus Y register data ADC AND CMP EOR LDA OR SBC STA Example G 0 Y 10H 1725 ADC 25H Y Absolute indirect abs The program jumps to address specified by 16 bit absolute address JMP Example G 0 1...

Страница 33: ...n Register R0ODC R0 Open Drain Assign Register R0ODC is 8bit register and can assign R0 port as open drain output port each bit if corresponding port is selected as output If R0ODC is se lected as 1 p...

Страница 34: ...acts as port R1 selection mode and when set as 1 it becomes function selection mode PMR1 is write only register and initialized as 00h in re set state Therefore becomes Port selection mode Port R1 can...

Страница 35: ...d The initial value of R2 is unknown in reset state 3 R2 Open drain Assign Register R2ODC R2 Open Drain Assign Register R2ODC is 8bit register and can assign R2 port as open drain output port each bit...

Страница 36: ...k to peripheral hardware can be stopped by bit4 EN PCK of CKCTLR Register ENPCK is set to 1 in reset state Clock Control Register W CKCTLR ADDRESS 0C7H INITIAL VALUE 110111b 0 1 2 3 4 5 6 7 ENPCK 0 St...

Страница 37: ...tion circuit is designed to be used either with a ce ramic resonator or crystal oscillator Since each crystal and ceramic resonator have their own characteristics the user should consult the crystal m...

Страница 38: ...ut open 2 0 3 6 MURATA CSTCC2M00G56 R0 Cin Cout open 2 0 3 6 4 00MHz CQ ZTT4 00 Cin Cout open 2 0 3 6 CQ ZTA4 00 Cin Cout 30pF 2 0 3 6 MURATA CSTS0400MG06 Cin Cout open 2 0 3 6 MURATA CSTLS4M00G56 B0...

Страница 39: ...and then after one machine cycle BTCL becomes 0 and B I T starts counting BTCL is set to 0 in reset state The input clock of B I T can be selected from the prescaler within a range of 2us to 256us by...

Страница 40: ...64 100 fXIN 128 101 fXIN 256 110 fXIN 512 111 fXIN 1024 Clear bit 0 Normal operation free run 1 Clear 8 bit counter BITR to 0 and count up again INITAIL VALUE 110111B ADDRESS 0C7H CKCTLR INITIAL VALU...

Страница 41: ...Request is used for input clock of WDT Input clock cycle is possible from 512 us to 65 536 us by BTS at fex 4MHz At Hardware reset time WDT starts automatically Therefore the user must select the CKCT...

Страница 42: ...event counter Timer0 16 bit Interval Timer 16 bit Event Counter 16 bit Input Capture 16 bit rectangular wave output Single Modulo N Mode Timer Output Initial Value Setting Timer0 Timer1 combination Lo...

Страница 43: ...r 01 mode register TOUT LOGIC 0 Timer1 output low 1 Timer1 output high Timer1 output initial value 0 T0OUT Polarity Equal to TOUT Logic input signal 1 T0OUT Polarity Reverse to TOUT Logic input signal...

Страница 44: ...Control 0 Timer Counter 1 Input capture PS1 not supporting Timer0 Interrupt select 0 Timer0 Stop 1 Tiemr0 Start after clear Timer0 Start Stop control R W R W CAP0 T0ST input capture 000 PS0 250ns 001...

Страница 45: ...INITIAL VALUE 00H ADDRESS 0D1H TM1 T1SL2 T1SL1 T1SL0 R W R W R W R W R W T1MOD Timer 1 mode register Timer1 input clock select fex 4Mhz 0 Modulo N 1 Single Mode 0 Interrupt Every Count Overflow 1 Inte...

Страница 46: ...2 PS12 T2 COUNT REG 0D9H T2DR BTCL 7 6 5 4 3 2 1 0 T2CN INITIAL VALUE 00H ADDRESS 0D2H TM2 T2SL2 T2SL1 T2SL0 R W R W R W R W R W Timer 2 mode register Timer2 input clock select fex 4Mhz 0 Count Pause...

Страница 47: ...ounter T0ST or T1ST should be temporarily set to 0 and then set to 1 T0CN T1CN T0ST and T1ST should be set 1 when Timer counting up Controlling of CAP0 enables Timer0 as input capture By programming o...

Страница 48: ...Stop Operation of Timer0 Timer 0 IFT0 Interrupt TDR TIME Occur interrupt Occur interrupt stop clear start disable enable Start Stop T0ST T0CN Control count u p c o u n t T0ST 0 T0ST 1 T0CN 0 T0CN 1 Fi...

Страница 49: ...f interrupt select bit T0IFS T1IFS of Mode Register is 0 Interrupt occurs on every Time out If it is 1 Interrupt occurs every second time out Note Timer Output is toggled whenever time out happen 4 Ti...

Страница 50: ...l is also possible Software inter rupt is non maskable interrupt the others are all maskable interrupts 8 interrupt source 2Ext 3Timer BIT WDT and Key Scan 8 interrupt vector Nested interrupt control...

Страница 51: ...lag is automatically cleared during interrupt cycle process The interrupt request flag maintains 1 until the interrupt is accepted or is cleared in program In reset state interrupt request flag regist...

Страница 52: ...isable 1 Enable VALUE R W INITIAL VALUE 000 000 B ADDRESS 0CEH IENH INT1E MSB LSB T0E T1E INT2E R W External interrupt 1 INITIAL VALUE 00 B ADDRESS 0CCH IENL MSB LSB Timer1 R W R W R W R W Basic Inter...

Страница 53: ...isabled 2 Interrupt request flag for the interrupt source accepted is cleared to 0 3 The contents of the program counter return address and the program status word are saved pushed onto the stack area...

Страница 54: ...ata memory area for saving registers The following method is used to save restore the general purpose registers Example Register save using push and pop instructions General purpose register save rest...

Страница 55: ...ser sets I flag in interrupt routine some further interrupt can be serviced even if certain interrupt is in progress Example During Timer1 interrupt is in progress INT1 interrupt serviced without any...

Страница 56: ...sources which release standby SLEEP STOP mode Key Scan ports are all 16bit which are controlled by Standby Mode Release Register SMRR0 SMRR1 Key Input is consid ered as Interrupt therefore KSCNE bit o...

Страница 57: ...R07 R00 R0 PORT LOGIC R13 R12 R11 R14 R15 R16 R17 R10 SMRR0 SRLC0 R1 PORT LOGIC SMRR1 SRLC1 Internal Key Scan Input W W W W W W W KR06 KR05 KR04 KR03 KR02 KR01 KR00 KR0 1 Select 0 No Select BTCL 7 6 5...

Страница 58: ...nter rupt bit10 of prescaler should be selected as B I T input clock before entering SLEEP mode NOP instruction should be follows setting of SLEEP mode for rising pre charge time of data bus line ex s...

Страница 59: ...on execution starts after stabi lization oscillation time is set by value of BTS2 BTS0 and set ENPCK to 1 Figure 15 1 Block Diagram of Standby Circuit OSC Circuit Clock Pulse Generator CPU Clock Relea...

Страница 60: ...Mask Enable flag 0 program executes from the next instruction of standby instruction When 1 enters each interrupt service routine Basic Interval Timer IFBIT When B I T is executed only by bit10 of pr...

Страница 61: ...levant interrupt service routine Note When STOP instruction is used B I T should guar antee the stabilization oscillation time Thus just before en tering STOP mode clock of bit10 PS10 of prescaler is...

Страница 62: ...Internal CPU Stop Stop Register Retained Retained RAM Retained Retained I O port Retained Retained Prescaler Active Stop Basic Interval Timer PS10 selected Active Others Stop Stop Watch dog Timer Stop...

Страница 63: ...until a crystal ceramic oscillator oscillates stably After power applies and starting of oscil lation this reset state is maintained for about oscillation cycle of 219 about 65 5ms at 4MHz The executi...

Страница 64: ...e Figure 16 2 Block Diagram of Power On Reset Circuit RESET GND 0 1uF GND VDD Internal Reset Power on Detect Pulse Generator OSC Circuit Prescaler Basic Interval Timer B I T Overflow Detection Circuit...

Страница 65: ...th Pull up resistor by Mask op tion If there is no information on the Mask option sheet the default pull up option all port connect to pull up resis tor is selected 3 Release of Low Voltage Detection...

Страница 66: ...e Remout port Low Level OSC STOP All I O port pull up on Mask Option SRAM Data retention until Fret Table 16 1 The operation after Low Voltage detection VDD 2V Min 1 7V typ 20 C 0 7V Vret 0V 3V about...

Страница 67: ...art example after Reset using SRAM Back up Figure 16 7 S W flow chart example after Reset using SRAM Back up RESET Check the SRAM value Stack Pointer initialize SRAM DATA VALID Use Saved SRAM value Cl...

Страница 68: ...14 R15 R16 R17 REMOUT RESET TEST R07 R06 R05 R04 VSS 1 2 3 4 5 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 6 14 13 24Pin 300mil width PDIP SOP R11 R10 VDD XOUT XIN R00 R01 R02 R03 R20 R16 R17 REMOUT...

Страница 69: ...ent AL AH VDD VDD VSS A0 A8 D0 A1 A9 D1 A2 A10 D2 A3 A11 D3 R20 1 2 3 4 5 7 8 9 10 11 12 13 14 6 WE VE RDE VSS VPP D7 A15 A7 D6 A14 A6 D5 A13 A5 D4 A12 A4 VSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15...

Страница 70: ...pull up resistor is disabled automatically Programmable key scan Input function LED driver include N TR Programmable open drain output Input Remain Input Output Input Remain 8bit CMOS input with pull...

Страница 71: ...EST RESET REMOUT R17 Input 25 R16 26 R15 27 R14 28 EPROM Mode Pin Name No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection VDD VDD VSS A0 A8...

Страница 72: ...H H H H H H H H LOCK Bit Read 11 5V H L H H H H Mode setting VPP RDE MS VE WE AL AH Remark PROM Write Verify 11 5V L H H H H L H H H L H L L H H H H H PROM Verify or Read 11 5V L H H H L H H H H L H L...

Страница 73: ...t IDD 100 mA VPPcurrent IPP 100 mA W E VIL VDDvoltage VDD 4 5 5 0 5 5 V VPPvoltage VPP 11 2 11 5 11 8 V VSSvoltage VSS 0 0 0 V GROUNDLevel Items Symbol Min Typ Max Unit High Address Setup Time tAHS 2...

Страница 74: ...IL 0 2 0 2 V Output high voltage VOH 0 7VDD V IOH 2 5mA Output low voltage VOL 0 4 V IOL 1mA VDDActive current IDD1 30 mA VE VIL Items Symbol Min Typ Max Unit High Address Setup Time tAHS 2 us High Ad...

Страница 75: ...Timing tAHS tAH tAHH tALS tAL tALH tWES tWE tWEH tVE tVEF tVED Mode setting 1Byte PGM Verify Repeat area 1 R0 7 0 address input is latched when AH R10 AL R11 is rising 2 R0 7 0 Data out DOUT is valid...

Страница 76: ...B VSS RESETB RDE REMOUT MS R20 R0 7 0 VE R17 WE R16 AL R11 AH R10 0V 0V 5V Min 50ms 11 5V Min 2us Min 10us H H H H H Latch Timing Latch Timing tAHS tAH tAHH tALS tAL tALH tVE tVEF tVED Mode setting Ve...

Страница 77: ...R20 R0 7 0 VE R17 WE R16 AL R11 AH R10 0V 0V 5V Min 50ms 11 5V Min 2us Min 10us H H H H L Latch Timing tAHS tAH tAHH tWES tWE tWEH Mode setting PGM 1 DIN 06XH LOCK bit Write Data X means don t care 2...

Страница 78: ...D VDD VPP TESTB VSS RESETB RDE REMOUT MS R20 R0 7 0 VE R17 WE R16 AL R11 AH R10 0V 0V 5V Min 50ms 11 5V Min 2us Min 10us H H H H L Latch Timing tAHS tAH tAHH Mode setting Lock bit Read DOUT tVE tVED t...

Страница 79: ...11 5V 0 3V Start Address n 0 n 1 n Data write tWE 200us 10 Verify Last Address Set EPROM write to Verify mode VDD 5 0 5 V VPP 11 5V VDD 2 7 0 2 V VPP 11 5V Verify all Address Device Pass Device Fail...

Страница 80: ...m temperature 17 9 REMOUT Port Iol Characteristics Graph typical process room temperature Figure 17 3 Ioh vs Voh 0 Ioh mA Voh V 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 5 10 15 20 25 30 Vdd 2V Vdd 3V Vdd 4V...

Страница 81: ...HMS8132E HMS81032TL Nov 2001 Ver 2 00 77 Figure 17 5 Low Voltage vs Temperature 1 4 1 5 1 6 1 7 1 8 1 9 2 0 25 20 15 10 5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 LVD V Temperature C...

Страница 82: ...frared LED Indicator LED R00 R01 R02 R03 R04 R05 R06 R07 R17 R16 R15 R14 R13 R12 R11 R10 1 2 3 4 5 6 7 8 9 10 11 13 12 15 14 16 18 19 21 20 23 22 24 17 26 27 29 28 31 30 32 25 34 35 37 36 39 38 40 33...

Страница 83: ...t Xin R00 R01 R02 R03 R20 TEST R07 R06 R05 R04 VSS R14 R15 R16 R17 REMOUT RESET 0 1uF 0 1uF DC 3V alkaline battery Infrared LED Indicator LED R00 R01 R02 R03 R04 R05 R06 R07 R17 R16 R15 R14 R13 R12 R1...

Страница 84: ...HMS81032E HMS81032TL 80 Nov 2001 Ver 2 00...

Страница 85: ...APPENDIX...

Страница 86: ...256 Customer should write inside thick line box This box is written after 6 Verification 28SOP 28SKDIP 24SOP 24SKDIP YYWW KOREA Customer s logo Customer logo is not required YYWW KOREA HMS810 Customer...

Страница 87: ...Register auto increment bit Bit Position A bit Bit Position of Accumulator dp bit Bit Position of Direct Page Memory M bit Bit Position of Memory Data 000H 0FFFH rel Relative Addressing Data upage U...

Страница 88: ...EI LDM dp imm STA dp STA dp X STA abs TAX STY dp TCALL 14 STC M bit STX dp STX dp Y XAX STOP LOW HIGH 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1...

Страница 89: ...X 19 2 5 20 ASL abs 18 3 5 21 CMP imm 44 2 2 Compare accumulator contents with memory contents A M 22 CMP dp 45 2 3 23 CMP dp X 46 2 4 24 CMP abs 47 3 4 N ZC 25 CMP abs Y 55 3 5 26 CMP dp X 56 2 6 27...

Страница 90: ...A A M 66 OR dp X 66 2 4 67 OR abs 67 3 4 N Z 68 OR abs Y 75 3 5 69 OR dp X 76 2 6 70 OR dp Y 77 2 6 71 OR X 74 1 3 72 ROL A 28 1 2 Rotate left through Carry 73 ROL dp 29 2 4 N ZC 74 ROL dp X 39 2 5 7...

Страница 91: ...F4 1 4 26 STA X FB 1 4 X register auto increment M A X X 1 27 STX dp EC 2 4 Store X register contents in memory 28 STX dp Y ED 2 5 M X 29 STX abs FC 3 5 30 STY dp E9 2 4 Store Y register contents in...

Страница 92: ...2 4 Bit test A with memory MM Z 4 BIT abs 1C 3 5 Z A M N M7 V M6 5 CLR1 dp bit y1 2 4 Clear bit M bit 0 6 CLRA1 A bit 2B 2 2 Clear A bit A bit 0 7 CLRC 20 1 2 Clear C flag C 0 0 8 CLRG 40 1 2 Clear G...

Страница 93: ...4 Branch if plus if N 0 then pc pc rel 11 BRA rel 2F 2 4 Branch always pc pc rel 12 BVC rel 30 2 2 4 Branch if overflow bit clear if V 0 then pc pc rel 13 BVS rel B0 2 2 4 Branch if overflow bit set...

Страница 94: ...NOP FF 1 2 No operation 5 POP A 0D 1 4 sp sp 1 A M sp 6 POP X 2D 1 4 sp sp 1 X M sp 7 POP Y 4D 1 4 sp sp 1 Y M sp 8 POP PSW 6D 1 4 sp sp 1 PSW M sp restored 9 PUSH A 0E 1 4 M sp A sp sp 1 10 PUSH X 2E...

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