HP Vectra VE5 3, Техническое справочное руководство

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16
2 System Board
Devices on the Processor-Local Bus
Cache Memory
The computer supports two levels of cache memory: Level-1 (L1), cache
memory, which is built into the processor chip, and Level-2 (L2) cache
memory, which is a slower, optional module on the system board. Each acts
as temporary storage for data and instructions from the main memory. Since
the system is likely to use the same data several times, it is faster to get it
from the on-chip or on-board cache memory than from the main memory.
The L1 cache memory is divided into two separate banks: an L1 I-cache for
instruction words, and an L1 D-cache for data words. Each has a capacity of
8 KB. The I-cache is two-way set-associative. The D-cache four-way set-
associative, and is configured for Write-Back on a line-by-line basis.
The L2 cache memory, when fitted, also has a 32-byte line width. It is
controlled by the PL/PCI bridge chip in the system board chip-set. A single
HP cache memory module consists of 256 KB of direct mapped,
synchronous pipelined burst, static random access memory (SRAM). The
synchronous cache memory module produces 10% better performance than
the asynchronous module.
The cache memory line width is 32-bytes, 256-bits, four times the width of
the Pentium’s Processor-Local data bus. Since reads and writes involve a full
cache line, they require four back-to-back cycles on the bus. The first cycle
in each burst of four always requires more time to complete than the three
subsequent cycles. This is because the first cycle includes the addressing
phase and memory pre-charge timing. The read and write access timing has
the pattern 3-1-1-1.
Fitting the optional cache memory module in its socket causes the
lowermost ISA slot to become partially blocked. Only half length boards
(17.5 cm / 7 inches) can then be fitted in this slot. Jumper J6 must be
connected between pins 2-3 for synchronous cache memory, and between
pins 1-2 for asynchronous cache memory.