HP Kayak XU700, Техническое справочное руководство

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2 System Board
Memory Controller Hub (82850)
AGP PCI Bus
Implementation
Main Memory Controller
The main memory controller is integrated in the MCH supporting two
primary rambus channels (A and B).
DRAM Interface
The MCH provides optional System bus error checking for data, address,
request and response signals. Only 400 MHz Direct Rambus devices are
supported in any of 128 or 256 Mbit technology. 128 Mbit RDRAM uses page
sizes of 1 kbytes, while 256 Mbit devices target 1 kbyte or 2 kbyte pages.
A maximum number of 32 Rambus devices (128 Mbit technology implies 1
GB maximum in 32 MB increments, 256 Mbit technology implies 2 GB
maximum in 64 MB increments) are supported on the Direct Rambus
channel without external logic.
The MCH also provides optional data integrity features including ECC in the
memory array. During DRAM writes, ECC is generated on a QWord (64 bit)
basis. During DRAM reads, the MCH supports multiple-bit error detection
and single-bit error correction when the ECC mode is enabled.
Pentium 4 Processor
GX-Device 1
AGP Port
Interface
PCI-to-PCI
Device 0
I850
Memory
Controller Hub
(MCH)
1.5V
AGP
PRO
Connector
AGP 4x Bus
(133 MHz)
Hub Link 8-bit
I/O Controller
Hub (ICH2)