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1-312

Propagation Delay, Pulse-
Width Distortion and
Propagation Delay Skew

Propagation delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga-
tion delay from low to high (t

PLH

)

is the amount of time required for
an input signal to propagate to
the output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (t

PHL

) is the

amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low (see
Figure 5).

Pulse-width distortion (PWD)
results when t

PLH

 and t

PHL

 differ in

value. PWD is defined as the
difference between t

PLH 

and t

PHL

and often determines the
maximum data rate capability of a
transmission system. PWD can be
expressed in percent by dividing
the PWD (in ns) by the minimum
pulse width (in ns) being
transmitted. Typically, PWD on
the order of 20-30% of the
minimum pulse width is tolerable;
the exact figure depends on the
particular application (RS232,
RS422, T-1, etc.).

Propagation delay skew, t

PSK

, is

an important parameter to
consider in parallel data applica-
tions where synchronization of
signals on parallel data lines is a
concern. If the parallel data is
being sent through a group of
optocouplers, differences in
propagation delays will cause the
data to arrive at the outputs of the
optocouplers at different times. If
this difference in propagation
delays is large enough, it will

determine the maximum rate at
which parallel data can be sent
through the optocouplers.

Propagation delay skew is defined
as the difference between the
minimum and maximum propaga-
tion delays, either t

PLH

 or t

PHL

, for

any given group of optocouplers
which are operating under the
same conditions (i.e., the same
drive current, supply voltage,
output load, and operating tem-
perature). As illustrated in
Figure 15, if the inputs of a group
of optocouplers are switched
either ON or OFF at the same
time, t

PSK

 is the difference

between the shortest propagation
delay, either t

PLH

 or t

PHL

, and the

longest propagation delay, either
t

PLH

 or t

PHL

.

As mentioned earlier, t

PSK

 can

determine the maximum parallel
data transmission rate. Figure 16
is the timing diagram of a typical
parallel data application with both
the clock and the data lines being
sent through optocouplers. The
figure shows data and clock
signals at the inputs  and  outputs  of
the optocouplers. To obtain the
maximum data transmission rate,
both edges of the clock signals
are being used to clock the data;
if only one edge were used, the
clock signal would need to be
twice as fast.

Propagation delay skew repre-
sents the uncertainty of where an
edge might be after being sent
through an optocoupler.
Figure 16 shows that there will be
uncertainty in both the data and
the clock lines. It is important
that these two areas of uncertainty
not overlap, otherwise the clock
signal might arrive before all of

the data outputs have settled, or
some of the data outputs may
start to change before the clock
signal has arrived. From these
considerations, the absolute
minimum pulse width that can be
sent through optocouplers in a
parallel application is twice t

PHZ

.

A cautious design should use a
slightly longer pulse width to
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.

The HCPL-2400/30 optocouplers
offer the advantages of guaran-
teed specifications for propaga-
tion delays, pulse-width distortion,
and propagation delay skew over
the recommended temperature,
input current, and power supply
ranges.

Application Circuit

A recommended LED drive circuit
is shown in Figure 13. This circuit
utilizes several techniques to
minimize the total pulse-width
distortion at the output of the
optocoupler. By using two
inverting TTL gates connected in
series, the inherent pulse-width
distortion of each gate cancels the
distortion of the other gate. For
best results, the two series-
connected gates should be from
the same package.

The circuit in Figure 13 also uses
techniques known as prebias and
peaking to enhance the
performance of the optocoupler
LED. Prebias is a small forward
voltage applied to the LED when
the LED is off. This small prebias
voltage partially charges the
junction capacitance of the LED,
allowing the LED to turn on more
quickly. The speed of the LED is
further increased by applying

Содержание HCPL-2400

Страница 1: ...CPL 5430 1 20 MBd High CMR Logic Gate Optocouplers Technical Data HCPL 2400 HCPL 2430 Applications Isolation of High Speed Logic Systems Computer Peripheral Interfaces Switching Power Supplies Isolated Bus Driver Networking Applications Ground Loop Elimination High Speed Disk Drive I O Digital Isolation for A D D A Conversion Pulse Transformer Replacement Functional Diagram CAUTION It is advised t...

Страница 2: ... The electrical and switching characteristics of the HCPL 2400 and HCPL 2430 are guaranteed over the temperature range of 0 C to 70 C These optocouplers are compatible with TTL STTL LSTTL and HCMOS logic families When Schottky type TTL devices STTL are used a data rate performance of 20 MBd over temperature is guaranteed when using the application circuit of Figure 13 Typical data rates are 40 MBd...

Страница 3: ...0 NOT MARKED Package Outline Drawings 8 Pin DIP Package HCPL 2400 HCPL 2430 8 Pin DIP Package with Gull Wing Surface Mount Option 300 HCPL 2400 HCPL 2430 0 635 0 25 0 025 0 010 12 NOM 9 65 0 25 0 380 0 010 0 635 0 130 0 025 0 005 7 62 0 25 0 300 0 010 5 6 7 8 4 3 2 1 9 65 0 25 0 380 0 010 6 350 0 25 0 250 0 010 1 016 0 040 1 194 0 047 1 194 0 047 1 778 0 070 9 398 0 370 9 906 0 390 4 826 0 190 TYP...

Страница 4: ...ut Tracking External terminals shortest distance path along body Creepage Minimum Internal 0 08 mm Through insulation distance conductor to Plastic Gap conductor usually the direct distance between the Internal Clearance photoemitter and photodetector inside the optocoupler cavity Tracking Resistance CTI 200 Volts DIN IEC 112 VDE 0303 Part 1 Comparative Tracking Index Isolation Group IIIa Material...

Страница 5: ...t Voltage Method a VIORM x 1 5 VPR Type and sample test VPR 945 V peak tm 60 sec Partial Discharge 5 pC Highest Allowable Overvoltage Transient Overvoltage tini 10 sec VIOTM 6000 V peak Safety Limiting Values Maximum values allowed in the event of a failure also see Figure 12 Thermal Derating curve Case Temperature TS 175 C Input Current IS INPUT 230 mA Output Power PS OUTPUT 600 mW Insulation Res...

Страница 6: ...0 V Output Voltage VO 0 5 18 V Output Collector Power Dissipation PO 40 mW Each Channel Total Package Power Dissipation PT 350 mW Each Channel Lead Solder Temperature 260 C for 10 sec 1 6 mm below seating plane for Through Hole Devices Reflow Temperature Profile See Package Outline Drawings section Option 300 Recommended Operating Conditions Parameter Symbol Minimum Maximum Units Power Supply Volt...

Страница 7: ...6 mA VCC 5 25 V VE 0 V IO Open 2430 34 46 VCC 5 25 V IO Open Logic High Supply ICCH 2400 17 26 mA VCC 5 25 V VE 0 V Current IO Open 2430 32 42 VCC 5 25 V IO Open High Impedance State ICCZ 2400 22 28 mA VCC 5 25 V VE 5 25 V Supply Current High Impedance State IOZL 2400 20 µA VO 0 4 V VE 2 V IOZH 20 µA VO 2 4 V IOZH 100 µA VO 5 25 V Logic Low Short Circuit IOSL 52 mA VO VCC 5 25 V 2 Output Current I...

Страница 8: ...7 mA 5 8 6 Distortion 5 25 Propagation Delay tPSK 35 ns Per Notes Text 15 16 7 Skew Output Rise Time tr 20 ns 5 Output Fall Time tf 10 ns 5 Output Enable Time tPZH 2400 15 ns 9 10 to Logic High Output Enable Time tPZL 2400 30 ns 9 10 to Logic Low Output Disable Time tPHZ 2400 20 ns 9 10 from Logic High Output Disable Time tPLZ 2400 15 ns 9 10 from Logic Low Logic High Common CMH 1000 10 000 V µs V...

Страница 9: ...ng edge of the output pulse 5 The typical data shown is indicative of what can be expected using the application circuit in Figure 13 6 This specification simulates the worst case operating conditions of the HCPL 2400 over the recommended operating temperature and VCC range with the suggested application circuit of Figure 13 7 Propagation delay skew is discussed later in this data sheet 8 Measured...

Страница 10: ...agation Delay vs Input Forward Current Figure 8 Typical Pulse Width Distortion vs Ambient Temperature Figure 5 Test Circuit for tPLH tPHL tr and tf Figure 1 Typical Logic Low Output Voltage vs Logic Low Output Current Figure 2 Typical Logic High Output Voltage vs Logic High Output Current Figure 3 Typical Output Voltage vs Input Forward Current ...

Страница 11: ...d Typical Waveforms Figure 12 Thermal Derating Curve Dependence of Safety Limiting Value with Case Temperature per VDE 0884 OUTPUT POWER P S INPUT CURRENT I S 0 0 TS CASE TEMPERATURE C 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 PS mW IS mA 175 0 1 µF VFF F I CC V GND NC NC CM V 7 5 6 8 2 3 4 1 C 15 pF A B PULSE GENERATOR L CC V OUTPUT V MONITORING NODE O HCPL 2400 11 ...

Страница 12: ...mended 20 MBd HCPL 2400 30 Interface Circuit Applications Figure 14 Alternative HCPL 2400 30 Interface Circuit Figure 16 Parallel Data Transmission Example Figure 17 Modulation Code Selections Figure 18 Typical HCPL 2400 30 Output Schematic DATA t PSK INPUTS CLOCK DATA OUTPUTS CLOCK t PSK HCPL 2400 HCPL 2400 V ...

Страница 13: ...or tPHL As mentioned earlier tPSK can determine the maximum parallel data transmission rate Figure 16 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers The figure shows data and clock signals at the inputs and outputs of the optocouplers To obtain the maximum data transmission rate both edges of the clock signals are...

Страница 14: ... worst case switching parameters given in the data sheet can be met using common 74LS TTL invert ing gates or buffers Use of faster TTL families will slightly reduce the overall propagation delays from the input of the drive circuit to the output of the optocoupler but will not necessarily result in lower pulse width distortion or propagation delay skew This reduction in overall propagation delay ...

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