HP E3472A, Руководство пользователя, Страница: 97 / 153

Table 8-8. Bus Timing (E3472A)
Characteristic Symbol SH7040 Typical
(*1)
Worst Case Unit
min max min max min max
Address delay time t
AD
(2) 18 - 9 - 23 ns
CS delay time 1 t
CSD1
(2) 21 - 11 - 26 ns
CS delay time 2 t
CSD2
(2) 21 - 8 - 26 ns
Read strobe delay time 1 t
RSD1
(2) 18 - 9 - 23 ns
Read strobe delay time 2 t
RSD2
(2) 18 - 7 - 23 ns
Read data setup time t
RDS
(15) - 15 - 25 - ns
Read data hold time t
RDH
0 - 0 - 0 - ns
Write strobe delay time 1 t
WSD1
(2) 18 - 11 - 23 ns
Write strobe delay time 2 t
WSD2
(2) 18 - 8 - 23 ns
Write data delay time t
WDD
- 35 - 14 - 40 ns
Write data hold time t
WDH
0 (10) 4 - -5 - ns
Wait setup time t
WTS
15 - 15 - 25 - ns
Wait hold time t
WTH
0 - 0 - 0 - ns
RAS delay time 1 t
RASD1
(2) 18 - 10 - 23 ns
RAS delay time 2 t
RASD2
(2) 18 - 7 - 23 ns
CAS delay time 1 t
CASD1
(2) 18 - 8 - 23 ns
CAS delay time 2 t
CASD2
(2) 18 - 6 - 23 ns
Read data access time t
ACC
39.6 - 39.6 - 29.6 - ns
RD to read data access time t
OE
22.2 - 22.2 - 12.2 - ns
Column address to read data access
time t
AA
39.6 - 39.6 - 29.6 - ns
RAS to read data access time t
RAC
57 - 57 - 47 - ns
CAS to read data access time t
CAC
4.8 - 4.8 - -5.2 - ns
Low address hold time t
RAH
2.4 - 12 - -2.6 - ns
Low address setup time t
ASR
-.1 - 12 - -5.1 - ns
*1 Typical outputs measured with 50pF load
Specifications and Characteristics
Electrical Specifications
82