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Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied. These can be masked
by resetting the EMI bit.
Interrupt Source
Priority
Vector
External Interrupt
1
04H
Timer/Event Counter Overflow
2
08H
In cases where both external and internal interrupts are enabled and where an external and inter-
nal interrupt occurs simultaneously, the external interrupt will always have priority and will there-
fore be serviced first. Suitable masking of the individual interrupts using the INTC register can
prevent simultaneous occurrences.
External Interrupt
An external interrupt is triggered by a high to low transition of the INT line, after which the related in-
terrupt request flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, the stack is not
full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt re-
quest flag EIF will be reset and the EMI bit will be cleared to disable other interrupts.
Timer/Event Counter Interrupt
The Timer/Event Counter interrupt is initialized when the Timer/Event Counter interrupt request
flag (TF; bit 5 of the INTC) is set, caused by a timer overflow. When the interrupt is enabled, the
stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related inter-
rupt request flag TF will be reset and the EMI bit cleared to disable further interrupts.
Programming Considerations
The Timer/Event Counters interrupt request flag TF, external interrupt request flag EIF, enable
Timer/Event Counter interrupt bit ETI, enable external interrupt bit EEI and enable master interrupt
bit EMI constitute an interrupt control register INTC which is located in the Data Memory. EMI, EEI
and ETI are used to control the enabling/disabling of interrupts. When disabled, these bits can pre-
vent the requested interrupt from being serviced. Once the interrupt request flags TF or EIF are
set, they will remain in the INTC register until the interrupts are serviced or cleared by a software in-
struction.
It is recommended that programs do not use the
²
CALL subroutine
²
within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or need to be serviced immediately in some appli-
cations. If only one stack is left and enabling the interrupt is not well controlled, the original control se-
quence will be damaged once a
²
CALL subroutine
²
is executed in the interrupt subroutine.
Chapter 1 Hardware Structure
33
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