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Holtek HT46R74D-1, Техническая документация

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Holtek HT46R74D-1 Скачать руководство пользователя страница 27

HT46R74D-1

Rev. 1.40

27

January 10, 2008

C O M 0 ,   C O M 1 ,   C O M 2

N o r m a l   O p e r a t i o n   M o d e  

D u r i n g   a   R e s e t   P u l s e

C O M 0 , C O M 1 , C O M 2  

V L C D  

1 / 2     V L C D  

V S S  
V L C D  

1 / 2     V L C D  

V S S  

A l l     L C D   d r i v e r   o u t p u t s  

C O M 0  

C O M 1  

C O M 2

*  

H A L T   M o d e  

V L C D  

1 / 2     V L C D  

V S S  

V L C D  

1 / 2     V L C D  

V S S  

V L C D  

1 / 2     V L C D  

V S S  

V L C D  

1 / 2     V L C D  

V S S  

V L C D  

1 / 2     V L C D  

V S S  

V L C D  

1 / 2     V L C D  

V S S  

V L C D  

1 / 2     V L C D  

V S S  
V L C D  

1 / 2     V L C D  

V S S  

V L C D  

1 / 2     V L C D  

V S S  

V L C D  

1 / 2     V L C D  

V S S  

V L C D  

1 / 2     V L C D  

V S S  

V L C D  

1 / 2     V L C D  

V S S  

V L C D

1 / 2     V L C D  

V S S  

*

*

*

N o t e :   "

*

"   O m i t     t h e   C O M 2   s i g n a l ,   i f   t h e   1 / 2   d u t y   L C D   i s   u s e d .

L C D   s e g m e n t s     O N

C O M 0 , 1 ,   2   s i d e s   a r e   u n l i g h t e d  

O n l y   L C D   s e g m e n t s   O N    

C O M 0   s i d e   a r e   l i g h t e d  
O n l y   L C D   s e g m e n t s   O N    

C O M 1   s i d e   a r e   l i g h t e d
O n l y   L C D   s e g m e n t s   O N    

C O M 2   s i d e   a r e   l i g h t e d

L C D   s e g m e n t s   O N

C O M 0 , 1   s i d e s   a r e   l i g h t e d  
L C D   s e g m e n t s   O N    

C O M 0 ,   2   s i d e s   a r e   l i g h t e d  

L C D   s e g m e n t s   O N

C O M 1 ,   2   s i d e s   a r e   l i g h t e d  
L C D   s e g m e n t s   O N  

C O M 0 , 1 ,   2   s i d e s   a r e   l i g h t e d  

A l l   l c d   d r i v e r   o u t p u t s

LCD Driver Output (1/3 Duty, 1/2 Duty, R Type)

LCD Display Memory

The device provides an area of embedded data memory
for the LCD display. This area is located at 40H to 4FH in
Bank 1 of the Data Memory. The bank pointer BP, en-
ables either the General Purpose Data Memory or LCD

Memory to be chosen. When BP is set to

²

1

²

, any data

written into location range 40H~4FH will affect the LCD

display. When the BP is cleared to

²

0

²

, any data written

into 40H~4FH will access the general purpose data
memory. The LCD display memory can be read and writ-
ten to only indirectly using MP1. When data is written
into the display data area, it is automatically read by the
LCD driver which then generates the corresponding

LCD driving signals. To turn the display on or off, a

²

1

²

or

a

²

0

²

is written to the corresponding bit of the display

memory, respectively. The figure illustrates the mapping
between the display memory and LCD pattern for the
device.

The LCD clock frequency is determined by configuration
options, and has a division ratio range of fs/2

2

~fs/2

8

.

The LCD clock source frequency should be chosen to
be as close as possible to 4kHz.

Note that the LCD frequency is controlled by configura-
tion options, which select the internal division ratio.

LCD Driver Output

The output number of the device LCD driver can be

16

´

2, 16

´

3 or 15

´

4 by configuration option (i.e., 1/2

duty, 1/3 duty or 1/4 duty). The bias type LCD driver can

be

²

R

²

type or

²

C

²

type. If the

²

R

²

bias type is selected,

no external capacitor is required. If the

²

C

²

bias type is

4 0 H

C O M

0

1

2

S E G M E N T

4 1 H

4 2 H

4 3 H

4 D H 4 E H

4 F H

B i t

0

1

2

3

1 3

1 4

1 5

3

0

1

2

3

Display Memory

Содержание HT46R74D-1

Страница 1: ...d voltage reference generator 1 5V 6 level subroutine nesting Bit manipulation instruction 15 bit table read instruction Up to 0 5ms instruction cycle with 8MHz system clock at VDD 5V 63 powerful instructions All instructions in 1 or 2 machine cycles Low voltage reset detector function 56 pin SSOP package General Description The HT46R74D 1 is an 8 bit high performance RISC architecture microcontro...

Страница 2: ... a l e r M U X W D T O S C R T C O S C f S Y S 4 T M R 0 C T M R 0 M U X T M R 1 C T M R 1 M U X P F D 0 P F D 1 f S Y S 4 f S Y S P r e s c a l e r P A 4 T M R 0 3 2 7 6 8 H z P A 5 T M R 1 D O P A P D O P A N D O P A O D C H O P D S R R D S R C D S C C O S C 3 O S C 4 P A 2 P A 3 P F D P A 4 T M R 0 P A 5 T M R 1 P A 6 I N T 0 P A 7 I N T 1 V S S V D D A V D D V O B G P C H P C 2 C H P C 1 V O C...

Страница 3: ...e configured as SEG15 SEG0 SEG14 O Segment Output LCD driver outputs for the LCD panel segments VOBGP AO Band gap voltage output pin for internal use VOREG O Regulator output 3 3V VOCHP O Charge pump output requires external capacitor CHPC1 Charge pump capacitor positive CHPC2 Charge pump capacitor negative DOPAN DOPAP DOPAO DCHOP AI AO Dual Slope converter pre stage OPA related pins DOPAN is the ...

Страница 4: ...Hz Analog block off 4 8 mA IDD4 Operating Current Crystal OSC 5V No load fSYS 8MHz Analog block off 4 8 mA IDD5 Operating Current RTC OSC 3V No load fSYS 32768Hz 0 3 0 6 mA 5V 0 6 1 mA IDD6 Operating Current ADC On 5V VREGO 3 3V fSYS 4MHz ADC on ADCCLK 125kHz all other analog devices off 3 5 mA ISTB1 Standby Current fS fSYS 4 3V No load system HALT Analog block off LCD off 1 mA 5V 2 mA ISTB2 Stand...

Страница 5: ...e Current 3V VOH 0 9VDD 2 4 mA 5V 5 10 mA IOL2 LCD Common and Segment Current 3V VOL 0 1VDD 210 420 mA 5V 350 700 mA IOH2 LCD Common and Segment Current 3V VOH 0 9VDD 80 160 mA 5V 180 360 mA RPH Pull high Resistance of I O Ports and INT 3V 20 60 100 kW 5V 10 30 50 kW Charge Pump and Regulator VCHPI Input Voltage Charge pump on 2 2 3 6 V Charge pump off 3 7 5 5 V VREGO Output Voltage No load 3 3 3 ...

Страница 6: ... fINRC Internal RC OSC 3V 12 kHz 5V 15 kHz fTIMER Timer I P Frequency TMR0 TMR1 2 2V 5 5V 0 4000 kHz tWDTOSC Watchdog Oscillator Period 3V 45 90 180 ms 5V 32 65 130 ms tRES External Reset Low Pulse Width 1 ms tSST System Start up Timer Period Power up or wake up from HALT 1024 tSYS tLVR Low Voltage Width to Reset 0 25 1 2 ms tINT Interrupt Pulse Width 1 ms Note tSYS 1 fSYS HT46R74D 1 Rev 1 40 6 Ja...

Страница 7: ...lates the program transfer by loading the address corresponding to each instruction The conditional skip is activated by instructions Once the condition is met the next instruction fetched during the current instruction execution is discarded and a dummy cycle replaces it to get a proper instruction oth erwise the program proceeds with the next instruction The lower byte of the Program Counter PCL...

Страница 8: ... and the stack is not full the program begins execution at location 018H Table location Any location in the Program Memory can be used as a look up table The instructions TABRDC m the current page 1 page 256 words and TABRDL m the last page transfer the contents of the lower order byte to the specified data memory and the contents of the higher order byte to the TBLH register which is the Table hi...

Страница 9: ...th BP set to a value of 01H using MP1 to indirectly read or write to the data memory areas with addresses from 40H 4FH will result in operations to Bank 1 Directly ad dressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of BP Indirect Addressing Register Locations 00H and 02H are indirect addressing regis ters that are not physically implemented Any read w...

Страница 10: ...e up function As an in terrupt is serviced a control transfer occurs by pushing the contents of the program counter onto the stack fol lowed by a branch to a subroutine at the specified loca tion in the Program Memory Only the contents of the program counter is pushed onto the stack If the con tents of the accumulator or of the status register is al tered by the interrupt service program which cor...

Страница 11: ...d by resetting the EMI bit Interrupt Source Priority Vector External interrupt 0 1 04H External interrupt 1 2 08H Timer Event Counter 0 overflow 3 0CH Timer Event Counter 1 overflow 4 10H ADC interrupt 5 14H Real time clock interrupt 6 18H Once an interrupt request flag has been set it remains in the INTC1 or INTC0 register until the interrupt is ser viced or cleared by a software instruction It i...

Страница 12: ...al components are required Although when the system enters the power down mode the sys tem clock stops the WDT oscillator keeps running with a period of approximately 65ms at 5V The WDT oscilla tor can be disabled by a configuration option to con serve power Watchdog Timer WDT The WDT clock is sourced from either its dedicated in ternal RC oscillator or from the instruction clock which is the syst...

Страница 13: ...e WDT If the CLR WDT1 and CLR WDT2 option is chosen i e CLR WDT times equal two these two instructions have to be executed to clear the WDT otherwise the WDT may reset the device due to a time out Bit No Label Function 0 1 WDTPWR0 WDTPWR1 WDT Power source selection 01 WDT power comes from VOCHP 10 WDT power comes from the regulator 00 11 WDT power comes from VOCHP strongly recommend use to use 01 ...

Страница 14: ... pins PA0 and PA1 to be used as normal I Os the second option is for both pins to be configured as BZ and BZ buzzer pins the third option selects only the PA0 pin to be used as a BZ buzzer pin with the PA1 pin re taining its normal I O pin function Note that the BZ pin is the inverse of the BZ pin which together generate a dif ferential output which can supply more power to con nected interfaces s...

Страница 15: ...override the con figuration option selection and force the pin to always behave as an input pin This arrangement enables the pin to be used as both a buzzer pin and as an input pin so regardless of the configuration option chosen the ac tual function of the pin can be changed dynamically by the application program by programming the appropri ate port control register bit Note The above drawing sho...

Страница 16: ...o sequences may occur If the related inter rupt is disabled or the interrupt is enabled but the stack is full the program will resume execution at the next instruction But if the interrupt is enabled and the stack is not full a regular interrupt response takes place When an interrupt request flag is set before entering the Power down mode the system cannot be awak ened using that interrupt If a wa...

Страница 17: ...LT Note u stands for unchanged To guarantee that the system oscillator has started and has stabilised the SST System Start up Timer provides an extra delay of 1024 system clock pulses when the system awakes from the Power down mode or during power up When awakening from the Power down mode or during a system power up the SST delay is added The functional unit chip reset status is shown below Progr...

Страница 18: ...00 0 1000 00 0 1000 00 0 1000 00 0 1000 uu u uuuu TMR1HH xx uu uu uu uu TMR1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 0000 1 0 0000 1 0 0000 1 0 0000 1 0 uuuu u 0 PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 uuuu PBC 1111 1111 1111 1111 uuuu A...

Страница 19: ...enable or disable and an active edge The T0M0 T0M1 TMR0C and T1M0 T1M1 TMR1C bits define the operation mode The event count mode is used to count external events which means that the clock source comes from an external pin TMR0 or TMR1 The timer mode functions as a normal timer with the clock source coming from the internally selected clock source Finally the pulse width measurement mode can be us...

Страница 20: ...N Defines if the 32768 Oscillator is running or not See Note 0 32768 Oscillator off if no other peripherals are using it 1 32768 Oscillator starts to run or keeps running 1 2 Unused bit read as 0 3 T1E Defines the timer event counter TMR1 active edge In the Event Counter Mode T1M1 T1M0 0 1 1 count on falling edge 0 count on rising edge In the Pulse Width measurement mode T1M1 T1M0 1 1 1 start coun...

Страница 21: ... CMOS outputs or Schmitt trigger inputs with or without pull high resistor structures can be reconfigured dynamically under software control To function as an input the corresponding latch of the control register must be written with a 1 The input source also depends on the control register If the con trol register bit is 1 the input will read the pad state To function as an output the the control...

Страница 22: ...s module named CHPRC The CHPRC is the Charge Pump Reg ulator Control register which controls the charge pump on off function the regulator on off functions as well as setting the clock divider value to generate the clock for the charge pump The CHPCKD4 CHPCKD0 bits are used to set the clock divider to generate the desired clock frequency for proper charge pump operation The actual frequency is det...

Страница 23: ...ll be enabled If the CHPEN bit is enabled the charge pump will be ac tive and will use VDD as its input to generate the double voltage output This double voltage will then be used as the input voltage for the regulator If CHPEN is set to 0 the charge pump is disabled and the charge pump out put will be equal to the charge pump input VDD It is necessary to carefully manage the VDD voltage If the vo...

Страница 24: ...rging behavior The ADCMPO bit is read only for the comparator output while the ADINTM bits can set the ADCMPO trigger mode for interrupt generation The following descriptions are based on the fact that ADRR0 0 The amplifier and buffer combination form a differential input pre amplifier which amplifies the sensor input signal The combination of the Integrator the comparator the resistor Rds between...

Страница 25: ...h 0 disable Power 1 Power source comes from the regulator 1 2 ADDISCH0 ADDISCH1 Defines the ADC discharge charge 00 reserved 01 charging Integrator input connect to buffer output 10 discharging Integrator input connect to VDSO 11 reserved 3 ADCMPO Dual Slope ADC last stage comparator output Read only bit write data instructions will be ignored During the discharging state when the integrator outpu...

Страница 26: ...nction is enabled the charging timer note 1 will auto start note 3 when the user sets ADDISCH to the charging mode The start method is determined by CHGCMP 0 disable 1 enable this auto function 6 ADISEN Dual slope auto discharge enable When this function enable and ADISCH is set to the charg ing mode and the charging timer note 1 run overflow the charging timer will auto stop note 3 and ADDISCH wi...

Страница 27: ... The device provides an area of embedded data memory for the LCD display This area is located at 40H to 4FH in Bank 1 of the Data Memory The bank pointer BP en ables either the General Purpose Data Memory or LCD Memory to be chosen When BP is set to 1 any data written into location range 40H 4FH will affect the LCD display When the BP is cleared to 0 any data written into 40H 4FH will access the g...

Страница 28: ...X connect to V1 LCD Segment pins used as Logic Outputs The SEG0 SEG7 pins also can be setup for use logic outputs using configuration options Once an LCD segment is selected for use as a logic output the content of bit 0 of the related segment address in the LCD RAM will appear on the segment SEG0 SEG7 are bits that can be individually optioned as logical outputs C O M 0 C O M 1 C O M 2 C O M 3 L ...

Страница 29: ...ng normal operation 2 Since a low voltage state has to be maintained in its original state for over 1ms therefore after the 1ms delay the device enters the reset mode The RTCC register definitions are listed below Bit No Label Function 0 2 RT0 RT2 8 to 1 multiplexer control inputs to select the real clock prescaler output 3 LVDC LVD enable disable 1 0 4 QOSC 32768Hz OSC quick start up function 0 1...

Страница 30: ...rce Wake up selection This option defines the wake up capability A falling edge on each external pin on PA has the capability to wake up the device from a Power Down condition Bit option Pull high selection Selects pull high resistors when the I O in in the input mode Bit options I O pins shared with other function selections PA0 BZ PA1 BZ PA0 and PA1 can be setup as I O pins or buzzer outputs PA3...

Страница 31: ...nected to the RES pin as short as possible to avoid noise interference HT46R74D 1 Rev 1 40 31 January 10 2008 H T 4 6 R 7 4 D 1 O S C 1 O S C 2 O S C C i r c u i t R E S 0 1 m F 1 0 0 k W V D D V S S 0 1 m F V D D 0 0 1 m F 1 0 k W S e e r i g h t s i d e D S R R D S R C D S C C V O R E G V O C H P V O B G P C H P C 1 C H P C 2 V S S S e n s o r V R E G 1 0 m F 1 0 m F 4 7 m F V R E G 1 0 m F D O ...

Страница 32: ...f add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out Care must be taken to en sure correct handling of carry and borrow data when re sults exceed 255 for addition and less than 0 for subtraction The increment and decrement instructions INC INCA DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination...

Страница 33: ...ctions Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be con sulted as a basic instruction reference using the follow ing listed conventions Table conventions x Bits immediate data m Data Memory address A Accumulator i 0 7 number of bits addr Program memory address Mnemonic Description Cycles Flag Affected Arithmetic A...

Страница 34: ...ro with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Table Read TABRDC m TABRDL m Read table current page to TBLH and Data Memory Read t...

Страница 35: ...lt is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform...

Страница 36: ...s None CLR WDT Clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in conjunc tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect Re petitively executing this instru...

Страница 37: ...9 or if the C flag is set then a value of 6 will be added to the high nibble Essentially the decimal conversion is performed by add ing 00H 06H 60H or 66H depending on the Accumulator and flag conditions Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H ...

Страница 38: ... addr Affected flag s None MOV A m Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator Operation ACC m Affected flag s None MOV A x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator Operation ACC x Affected flag s None MOV m A Move ACC to Data Memory Description The contents of the Accumulator ...

Страница 39: ...continues at the restored address Operation Program Counter Stack ACC x Affected flag s None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re enabled by set ting the EMI bit EMI is the master interrupt global enable bit If an interrupt was pending when the RETI instruction is executed the pending Interrupt routine will be processed be ...

Страница 40: ... flag s None RRA m Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro tated into bit 7 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i m i 1 i 0 6 ACC 7 m 0 Affected flag s None RRC m Rotate Data Memory right through Carry Descripti...

Страница 41: ...are first decremented by 1 If the result is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SDZA m Skip if decrement Data Memory is zero with result in ACC Descrip...

Страница 42: ...hile the next instruction is fetched it is a two cycle instruction If the result is 0 the program proceeds with the following instruction Operation Skip if m i 0 Affected flag s None SUB A m Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator The result is stored in the Accumulator Note that if the result of subtraction is negative...

Страница 43: ...this requires the insertion of a dummy instruc tion while the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation ACC m Skip if m 0 Affected flag s None SZ m i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0 the following instruction is skipped As this re quires the i...

Страница 44: ...emory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op eration The result is stored in the Data Memory Operation m ACC XOR m Affected flag s Z XOR A x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation The result is stored in the Accumulator Operation ACC AC...

Страница 45: ... pin SSOP 300mil Outline Dimensions Symbol Dimensions in mil Min Nom Max A 395 420 B 291 299 C 8 12 C 720 730 D 89 99 E 25 F 4 10 G 25 35 H 4 12 a 0 8 HT46R74D 1 Rev 1 40 45 January 10 2008 5 6 1 A 2 9 2 8 B C D F C H a E G ...

Страница 46: ...6641 7752 Fax 86 10 6641 0125 Holtek Semiconductor Inc Chengdu Sales Office 709 Building 3 Champagne Plaza No 97 Dongda Street Chengdu Sichuan China 610016 Tel 86 28 6653 6590 Fax 86 28 6653 6591 Holtek Semiconductor USA Inc North America Sales Office 46729 Fremont Blvd Fremont CA 94538 Tel 1 510 252 9880 Fax 1 510 252 9885 http www holtek com Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC The infor...

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