Holtek HT46R74D-1, Техническая документация, Страница: 11 / 46

HT46R74D-1
Rev. 1.40 11 January 10, 2008
manner but its related interrupt request flag is T1F,
which is bit 4 of INTC1, and its subroutine call location is
10H.
The A/D converter interrupt is generated when the A/D
converter interrupt request flag, ADF; bit 5 of INTC1 is
set. This occurs when an A/D conversion process has
completed. After the interrupt is enabled, if the stack is
not full, and the ADF bit is set, a subroutine call to loca-
tion 14H occurs. The related interrupt request flag, ADF,
is reset and the EMI bit is cleared to disable further
maskable interrupts.
The real time clock interrupt is generated when the real
time clock interrupt request flag, RTF; bit 6 of INTC1, is
set. After the interrupt is enabled, if the stack is not full,
and the RTF bit is set, a subroutine call to location 18H
occurs. The related interrupt request flag, RTF, is reset
and the EMI bit is cleared to disable further maskable in-
terrupts.
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the
²
RETI
²
instruction is executed or the EMI bit and the
related interrupt control bit are set both to 1 (if the stack
is not full). To return from the interrupt subroutine, a
²
RET
²
or
²
RETI
²
instruction may be invoked. A RETI
instruction sets the EMI bit and enables an interrupt ser-
vice, but a RET instruction does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Interrupt Source Priority Vector
External interrupt 0 1 04H
External interrupt 1 2 08H
Timer/Event Counter 0 overflow 3 0CH
Timer/Event Counter 1 overflow 4 10H
ADC interrupt 5 14H
Real time clock interrupt 6 18H
Once an interrupt request flag has been set, it remains
in the INTC1 or INTC0 register until the interrupt is ser-
viced or cleared by a software instruction.
It is recommended that a program should not use the
²
CALL subroutine
²
within the interrupt subroutine. This is
because interrupts often occur in an unpredictable man-
ner or require to be serviced immediately in some appli-
cations. During that period, if only one stack is left, and
enabling the interrupts is not well controlled, executing a
²
call
²
in the interrupt subroutine may damage the origi-
nal control sequence.
Bit No. Label Function
0 EMI Control the master (global) interrupt (1=enabled; 0=disabled)
1 EEI0 Control the external interrupt 0 (1=enabled; 0=disabled)
2 EEI1 Control the external interrupt 1 (1=enabled; 0=disabled)
3 ET0I Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
4 EIF0 External interrupt 0 request flag (1=active; 0=inactive)
5 EIF1 External interrupt 1 request flag (1=active; 0=inactive)
6 T0F Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
7
¾
For test mode used only.
Must be written as
²
0
²
; otherwise may result in unpredictable operation.
INTC0 (0BH) Register
Bit No. Label Function
0 ET1I Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
1 EADI Control the ADC interrupt (1=enabled; 0:disabled)
2 ERTI Control the real time clock interrupt (1=enabled; 0:disabled)
3, 7
¾
Unused bit, read as
²
0
²
4 T1F Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
5 ADF ADC request flag (1=active; 0=inactive)
6 RTF Real time clock request flag (1=active; 0=inactive)
INTC1 (1EH) Register