Rev. 1.00
36
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Rev. 1.00
37
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HT46R003B
Cost-Effective A/D 8-bit OTP MCU
HT46R003B
Cost-Effective A/D 8-bit OTP MCU
Timer Register – TMR
The timer register is special function register located in the Special Purpose Data Memory and is the
place where the actual timer value is stored. The register is known as TMR. The value in the timer
register increases by one each time an internal clock pulse is received or an external transition occurs
on the external timer pin. The timer will count from the initial value loaded by the preload register to
the full count of FFH at which point the timer overflows and an internal interrupt signal is generated.
The timer value will then reset with the initial preload register value and continue counting.
Note that to achieve a maximum full range count of FFH, the preload register must first be cleared.
It should be noted that after power-on, the preload register will be in an unknown condition. Note
that if the Timer/Event Counter is in an OFF condition and data is written to its preload register,
this data will be immediately written into the actual counter. However, if the counter is enabled and
counting, any new data written into the preload data register during this period will remain in the
preload register and will only be written into the actual counter the next time an overflow occurs.
Timer Control Register – TMRC
The flexible features of the Holtek microcontroller Timer/Event Counter enable it to operate in three
different modes, the options of which are determined by the contents of their respective control
register.
The Timer Control Register is known as TMRC. It is the Timer Control Register together with its
corresponding timer register that controls the full operation of the Timer/Event Counter. Before
the timer can be used, it is essential that the Timer Control Register is fully programmed with the
right data to ensure its correct operation, a process that is normally carried out during program
initialization.
To select which of the three modes the timer is to operate in, either in the timer mode, the event
counting mode or the pulse width capture mode, bits 7 and 6 of the Timer Control Register, which
are known as the bit pair TM1/TM0, must be set to the required logic levels. The timer-on bit, which
is bit 4 of the Timer Control Register and known as TON, provides the basic on/off control of the
respective timer. Setting the bit to high allows the counter to run. Clearing the bit stops the counter.
Bits 0~2 of the Timer Control Register determine the division ratio of the input clock prescaler. The
prescaler bit settings have no effect if an external clock source is used. If the timer is in the event
count or pulse width capture mode, the active transition edge level type is selected by the logic level
of bit 3 of the Timer Control Register which is known as TEG.
TMRC Register
Bit
7
6
5
4
3
2
1
0
Name
TM1
TM0
—
TON
TEG
TPSC�
TPSC1
TPSC0
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
POR
0
0
—
0
1
0
0
0
Bit 7~6
TM1~TM0
: Timer operation mode selection
00: No mode available
01: Event counter mode
10: Timer mode
11: Pulse width capture mode
Bit 5
Unimplemented, read as "0"
Bit 4
TON
: Timer/event counter counting enable
0: Disable
1: Enable