Hitachi HTDK170EUK, Руководство по обслуживанию

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VID_SCN_HBLANK_STOP
The write-only Video Screen Horizontal Blanking Interval End Address register contains the 13-bit
ending address of the horizontal blanking stop interval for the active video display.
VID_SCN_VBLANK_START
The Video Screen Vertical Blanking Interval Start Address register contains the 13-bit starting
address of the vertical blanking interval for the active video display.
VID_SCN_VBLANK_STOP
The write-only Video Screen Vertical Blanking Interval Stop Address register contains the 13-bit
ending address of the vertical blanking stop interval for the active video display.
VID_SCN_HSYNCWIDTH
The write-only Video Screen Horizontal Sync Width Pulse register contains the 13-bit value of the
horizontal sync pulse width for the active video display. This register is needed only if sync
direction is output
VID_SCN_HSYNCPERIOD
The write-only Video Screen Horizontal Sync Period register contains the 13-bit value for the
period of the horizontal sync pulse used by the active video display. It is needed only if sync
direction is output.
VID_SCN_VSYNCPERIOD
The write-only Video Screen Video Sync Period register contains the 13-bit value for the period of
the vertical sync pulse used by the active video display. This register is needed only if sync
direction is output.
VID_SCN_VSYNCPIXEL
The write-only Video Screen Vertical Sync Pixel register defines which pixel VSYNC will change
on for the active video display. The number of pixels delayed from HSYNC that VSYNC will
change on either the rising or falling edge of VSYNC. This register is needed only if sync direction
is output
VID_SCN_VSYNCWIDTH
The write-only Video Screen Vertical Sync Pulse Width register defines the width of the 6-bit
vertical sync pulse. It is needed only if sync direction is output
VID_SCN_VERTCOUNT
The read-only Video Screen Verital Counter register contains the current line of the vertical
counter, and starts its counting at VSYNC line 0. This register is typically used for testing only.
VID_SCN_HORIZCOUNT
The read-only Video Screen Horizontal Counter register contains the current pixel of the
horizontal counter, and starts its counting at HSYNC pixel 0. This register is typically used for
testing only.
VID_SCN_COUNTER_CTL
The write-only Video Screen Counter Control register contains counter control bits for the inverted
blank sync, inverted horizontal sync, and inverted vertical sync functions. This register initializes
to 0x00 after reset.
VID_SCN_OUTPUTCNTL
The Video Screen Output Control register contains the control logic used to control the clamping
and filtering characteristics of the signal being output to the video display.