Hitachi DVC-605U, Руководство по обслуживанию

Страница: 10 / 126

Reference Information
2-3
No.
Pin Name
Description
I/O
Notes
Notes
1
DVSS
Digital GND (0 V)
2
ZCS_IN
Chip
Select
(Active
Low)
I
M
ICOM
3
MRZA_IN
Micom Register Select (L
REGISTER H
fi
D
A
T
A
)
I
MICOM
4
DVSS
Digital GND (0 V)
5
M
DA
T7_BI
M
ICO
M Data Bus
B
M
ICOM
6
M
DA
T6_BI
M
ICO
M Data Bus
B
M
ICOM
7
M
DA
T5_BI
M
ICO
M Data Bus
B
M
ICOM
8
M
DA
T4_BI
M
ICO
M Data Bus
B
M
ICOM
9
M
DA
T3_BI
M
ICO
M Data Bus
B
M
ICOM
1
0
MDA
T2_BI
M
ICO
M Data Bus
B
M
ICOM
1
1
MDA
T1_BI
M
ICO
M Data Bus
B
M
ICOM
1
2
MDA
T0_BI
M
ICO
M Data Bus
B
M
ICOM
1
3
DVDD
Digital Power (+5V)
14
XTI_IN
System Clock Input for 26.16 MHz
I
X
T
A
L
1
5
XT
O_OUT
System Clock Output for 26.16 MHz
O
X
T
A
L
16
DVSS
Digital GND (0 V)
1
7
DD15_BI
DRAM Data Bus
B
DRAM
1
8
DD0_BI
DRAM Data Bus
B
DRAM
1
9
DD14_BI
DRAM Data Bus
B
DRAM
2
0
DD1_BI
DRAM Data Bus
B
DRAM
21
DVSS
Digital GND (0 V)
2
2
DD13_BI
DRAM Data Bus
B
DRAM
2
3
DD2_BI
DRAM Data Bus
B
DRAM
2
4
DD12_BI
DRAM Data Bus
B
DRAM
2
5
DD3_BI
DRAM Data Bus
B
DRAM
2
6
DVDD
Digital Power (+5 V)
2
7
D
D
1
1_BI
Digital Data Bus
B
DRAM
2
8
DD4_BI
Digital Data Bus
B
DRAM
2
9
DD10_BI
Digital Data Bus
B
DRAM
3
0
DD5_BI
Digital Data Bus
B
DRAM
31
DVSS
Digital GND (0 V)
3
2
DD9_BI
DRAM Data Bus
B
DRAM
3
3
DD6_BI
DRAM Data Bus
B
DRAM
3
4
DD8_BI
DRAM Data Bus
B
DRAM
3
5
DD7_BI
DRAM Data Bus
B
DRAM
36
DVSS
Digital GND (0 V)
3
7
ZLCAS_OUT
DRAM Low Column Address Strobe
O
DRAM
3
8
ZUCAS_OUT
DRAM Upper Column Address Strobe
O
DRAM
3
9
ZWE1_OUT
DRAM
W
rite
Enable 1
(8M
ONL
Y
)
O
DRAM
4
0
ZWE0_OUT
DRAM
W
rite
Enable
0
(4M,
8M,
16M)
O
DRAM
4
1
ZOE1_OUT
DRAM Output Enable 1 (16M MODE DADR9)
O
DRAM
4
2
DVDD
Digital Power (+5 V)
4
3
ZOE0_OUT
DRAM Output Enable 0
O
DRAM
4
4
ZRAS_OUT
DRAM Row Address Strobe
O
DRAM
4
5
DADR8_OUT
DRAM Address Bus
O
DRAM
65
SDA
T
A5_OUT
DVD Data/Subcode Frame Sync (WFSY)
O
A
V
Decoder
66
SDA
T
A6_OUT
DVD Data/Subcode
Block
Sync
(S0S1)
O
A
V
Decoder
67
SDA
T
A7_BI
DVD Data/Subcode Serial Clock (SQCK)
B
A
V
Decoder
68
DVSS
Digital GND (0 V)
69
CSTROBE_OUT
Data Strobe (Clock) Output
O
A
V
Decoder
70
DA
TREQ_IN
Data Request from A/V Decoder or ROM Decoder
I
A
V
Decoder
7
1
DTER_OUT
DVD Data Error Output
O
A
V
Decoder
72
DVSS
Digital GND (0 V)
73
PWMO7_OUT
PWM Output Signal
O
R
F
74
PWMO6_OUT
PWM Output Signal
O
R
F
75
PWMO5_OUT
PWM Output Signal
O
R
F
76
PWMO4_OUT
PWM Output Signal
O
R
F
77
DVDD
Digital Power (+5 V)
78
PWMO3_OUT
PWM Output Signal
O
R
F
79
PWMO2_OUT
PWM Output Signal
O
R
F
80
PWMO1_OUT
PWM Output Signal
O
R
F
81
PWMO0_OUT
PWM Output Signal
O
R
F
82
DVSS
Digital GND (0 V)
83
DVSS
Digital GND (0 V)
84
DVSS
Digital GND (0 V)
8
5
DVDD
DIGIT
AL
Power
(+5
V)
8
6
DVDD
DIGIT
AL
Power
(+5
V)
87
DVSS
Digital GND (0 V)
88
DVSS
Digital GND (0 V)
89
DVSS
Digital GND (0 V)
90
DVSS
Digital GND (0 V)
91
FRSYZ_OUT
Frame Sync Out
O
Monitor
92
TX_OUT
Digital Out
O
M
onitor
No.
Pin Name
Description
I/O
46
DADR7_OUT
DRAM
Address
Bus
O
DRAM
47
DVSS
Digital GND (0 V)
48
DADR0_OUT
DRAM
Address
Bus
O
DRAM
49
DADR6_OUT
DRAM
Address
Bus
O
DRAM
50
DADR1_OUT
DRAM
Address
Bus
O
DRAM
51
DADR5_OUT
DRAM
Address
Bus
O
DRAM
52
DADR2_OUT
DRAM
Address
Bus
O
DRAM
53
DADR4_OUT
DRAM
Address
Bus
O
DRAM
54
DADR3_OUT
DRAM
Address
Bus
O
DRAM
55
DVSS
Digital GND (0 V)
56
DVSS
Digital GND (0 V)
57
T
OS_OUT
T
op
of
Sector
O
A
V
Decoder
5
8
DA
T
ACK_OUT
Data Acknowledge Signal Output
O
A
V
Decoder
59
DVDD
DIGIT
A
L
Power (+5 V)
60
SDA
T
A0_OUT
DVD
Data/CD
Data
Bit
Stream
(CDA
T
A)
O
A
V
Decoder
61
SDA
T
A1_OUT
DVD Data/CD Data L/R Clock (LRCK)
O
A
V
Decoder
62
SDA
T
A2_OUT
DVD
Data/CD Data
Bit
Clock
(BLCK)
O
A
V
Decoder
63
SDA
T
A3_OUT
DVD
Data/CD Data
Error
Flag
(C2PO)
O
A
V
Decoder
64
SDA
T
A4_OUT
DVD Data/Subcode
Serial
Data (SQDT)
O
A
V
Decoder
93
GFS_OUT
Good Frame Sync Detection State Output (OK at H)
O
M
onitor
94
DVSS
Digital GND (0 V)
95
CK33MI_IN
System Clock Input for 33.8688 MHz
I
X-tal
96
CK33MO_OUT
System
Clock
Output
for
33.8688
MHz
O
X-tal
9
7
DVDD
Digital Power (+5 V)
9
8
TEST0_IN
T
est Mode Selection T
erminal
I
9
9
TEST1_IN
T
est Mode Selection T
erminal I
100
TEST2_IN
T
est Mode Selection T
erminal
I
101
EFMO_OUT
EFM Out
O
M
onitor
102
WFCK_OUT
W
rite Frame
Pulse
O
M
onitor
103
RFCK_OUT
Reference Frame Pulse
O
M
onitor
104
PLCK_IN
Phase Locked Clock
I
Servo
105
DVSS
Digital GND (0 V)
106
PLLLOCK_OUT
Lock Signal for PLL
O
Servo
107
CL
VLOCK_OUT
Lock Signal for CL
V
O
Monitor
108
SERLOCK_OUT
Lock Signal for SER
VO
O
Servo
109
MDP_OUT
Spindle Motor Phase Control Signal (3-ST
A
TE)
O
Servo
11
0
M
DS_OUT
Spindle Motor Speed Control Signal (3-ST
A
TE)
O
Servo
11
1
DVSS
Digital GND (0 V)
11
2
DVSS
Digital GND (0 V)
11
3
MON_OUT
Spindle Motor Output Filter Switching Output
O
Servo
11
4
FG_IN
Reference Signal for CA
V
I
Servo
11
5
FSW_OUT
Spindle Motor Output Filter Switching Output (3-ST
A
TE)
O
Servo
11
6
EFMI_IN
EFM/EFM+ Signal Input
I
Servo
11
7
DVDD
Digital Power (+5 V)
11
8
DVDD
Digital Power (+5 V)
11
9
DVDD
Digital Power (+5 V)
120
CK16M_OUT
CK33M
s 2 Division Clock / 16.9344 MHz
O
Monitor
121
DEMPHA_OUT
HIGH
, when on Deemphasis
O
M
onitor
122
BCARZ_IN
BCA
Input
Signal
I
R
F
123
DVSS
Digital GND (0 V)
124
ZRST_IN
Hardware Reset (Active Low)
I
MICOM
125
ZW
AIT_OUT
Micom
Read
/
W
rite
Access
W
ait
(W
ait
at
L)
O
MICOM
126
ZIRQZD_OUT
Interrupt Request to Micom
O
MICOM
127
MRD_IN
Micom Read Strobe (Active Low)
I
MICOM
128
MWR_IN
Micom W
rite
Strobe (Active Low)
I
MICOM
Notes