Hitachi 32LD8600, Руководство по обслуживанию

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1
TFT TV Service Manual
1. INTRODUCTION
TFT TV is a progressive TV control system with built-in de-interlacer and scaler . It uses a
1366*768 panel with 16:9 aspect ratio. The TV is capable of operation in PAL, SECAM, NTSC
(playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including
German and NICAM stereo. Sound system output is supplying 2x8W (10%THD) for stereo 8
ȍ
speakers. The chassis is equipped with many inputs and outputs allowing it to be used as a center of a
media system.
It supports
the
following peripherals:
2 SCART sockets
1 AV input (CVBS + Stereo Audio)
1 SVHS input
1 Stereo Headphone input
1 Component input (YPbPr + Stereo Audio)
1 D-Sub 15 PC input
1 HDMI input
1 Stereo audio input for PC
Audio line out is taken from the scart with given scart-to-line out connector
2. TUNER
The tuners used in the design are combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L’,
I/I’, and D/K. The tuning is available through the digitally controlled I
2
C bus (PLL). Below you will find
info on one of the Tuners in use.
General description of UV1316:
The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of
applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low
IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient
suppression of triple transient.
Features of UV1316:
1. Member of the UV1300 family small sized UHF/VHF tuners
2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K
3. Digitally controlled (PLL) tuning via I
2
C-bus
4. Off-air channels, S-cable channels and Hyper band
5. World standardised mechanical dimensions and world standard pinning
6. Compact
size
7. Complies to “CENELEC EN55020” and “EN55013”
Pinning:
1. Gain control voltage (AGC) : 4.0V, Max: 4.5V
2. Tuning voltage
3. I²C-bus address select : Max: 5.5V
4. I²C-bus serial clock : Min:-0.3V, Max: 5.5V
5. I²C-bus serial data : Min:-0.3V, Max: 5.5V
6. Not connected
7. PLL supply voltage : 5.0V, Min: 4.75V, Max: 5.5V
8. ADC input
9. Tuner supply voltage : 33V, Min: 30V, Max: 35V
10. Symmetrical IF output 1
11. Symmetrical IF output 2
3. IF PART (TDA9886)
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal
PLL. The following figure shows the simplified block diagram of the integrated circuit.
The integrated circuit comprises the following functional blocks:
VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector,
VCO and divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap,
SIF amplifier, SIF-AGC detector, Single reference QSS mixer, AM demodulator, FM demodulator and